| /kernel/linux/linux-5.10/net/netlabel/ |
| D | netlabel_addrlist.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * NetLabel Network Address Lists
5 * This file contains network address list functions used to manage ordered
10 * Author: Paul Moore <paul@paul-moore.com>
14 * (c) Copyright Hewlett-Packard Development Company, L.P., 2008
32 * Address List Functions
36 * netlbl_af4list_search - Search for a matching IPv4 address entry
37 * @addr: IPv4 address
41 * Searches the IPv4 address list given by @head. If a matching address entry
52 if (iter->valid && (addr & iter->mask) == iter->addr) in netlbl_af4list_search()
[all …]
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| D | netlabel_domainhash.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * Author: Paul Moore <paul@paul-moore.com>
14 * (c) Copyright Hewlett-Packard Development Company, L.P., 2006, 2008
55 * netlbl_domhsh_free_entry - Frees a domain hash table entry
56 * @entry: the entry's RCU field
60 * function so that the memory allocated to a hash table entry can be released
64 static void netlbl_domhsh_free_entry(struct rcu_head *entry) in netlbl_domhsh_free_entry() argument
74 ptr = container_of(entry, struct netlbl_dom_map, rcu); in netlbl_domhsh_free_entry()
75 if (ptr->def.type == NETLBL_NLTYPE_ADDRSELECT) { in netlbl_domhsh_free_entry()
77 &ptr->def.addrsel->list4) { in netlbl_domhsh_free_entry()
[all …]
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| /kernel/linux/linux-6.6/net/netlabel/ |
| D | netlabel_addrlist.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * NetLabel Network Address Lists
5 * This file contains network address list functions used to manage ordered
10 * Author: Paul Moore <paul@paul-moore.com>
14 * (c) Copyright Hewlett-Packard Development Company, L.P., 2008
32 * Address List Functions
36 * netlbl_af4list_search - Search for a matching IPv4 address entry
37 * @addr: IPv4 address
41 * Searches the IPv4 address list given by @head. If a matching address entry
52 if (iter->valid && (addr & iter->mask) == iter->addr) in netlbl_af4list_search()
[all …]
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| D | netlabel_domainhash.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * Author: Paul Moore <paul@paul-moore.com>
14 * (c) Copyright Hewlett-Packard Development Company, L.P., 2006, 2008
55 * netlbl_domhsh_free_entry - Frees a domain hash table entry
56 * @entry: the entry's RCU field
60 * function so that the memory allocated to a hash table entry can be released
64 static void netlbl_domhsh_free_entry(struct rcu_head *entry) in netlbl_domhsh_free_entry() argument
74 ptr = container_of(entry, struct netlbl_dom_map, rcu); in netlbl_domhsh_free_entry()
75 if (ptr->def.type == NETLBL_NLTYPE_ADDRSELECT) { in netlbl_domhsh_free_entry()
77 &ptr->def.addrsel->list4) { in netlbl_domhsh_free_entry()
[all …]
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| /kernel/linux/linux-5.10/arch/sh/mm/ |
| D | tlbex_32.c | 5 * Copyright (C) 2003 - 2012 Paul Mundt
23 unsigned long address) in handle_tlbmiss() argument
30 pte_t entry; in handle_tlbmiss() local
35 * 29-bit mode, or due to PMB configuration in 32-bit mode. in handle_tlbmiss()
37 if (address >= P3SEG && address < P3_ADDR_MAX) { in handle_tlbmiss()
38 pgd = pgd_offset_k(address); in handle_tlbmiss()
40 if (unlikely(address >= TASK_SIZE || !current->mm)) in handle_tlbmiss()
43 pgd = pgd_offset(current->mm, address); in handle_tlbmiss()
46 p4d = p4d_offset(pgd, address); in handle_tlbmiss()
49 pud = pud_offset(p4d, address); in handle_tlbmiss()
[all …]
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| /kernel/linux/linux-6.6/arch/sh/mm/ |
| D | tlbex_32.c | 5 * Copyright (C) 2003 - 2012 Paul Mundt
23 unsigned long address) in handle_tlbmiss() argument
30 pte_t entry; in handle_tlbmiss() local
35 * 29-bit mode, or due to PMB configuration in 32-bit mode. in handle_tlbmiss()
37 if (address >= P3SEG && address < P3_ADDR_MAX) { in handle_tlbmiss()
38 pgd = pgd_offset_k(address); in handle_tlbmiss()
40 if (unlikely(address >= TASK_SIZE || !current->mm)) in handle_tlbmiss()
43 pgd = pgd_offset(current->mm, address); in handle_tlbmiss()
46 p4d = p4d_offset(pgd, address); in handle_tlbmiss()
49 pud = pud_offset(p4d, address); in handle_tlbmiss()
[all …]
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| /kernel/linux/linux-6.6/arch/arm/mm/ |
| D | cache-fa.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/cache-fa.S
6 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
8 * Based on cache-v4wb.S:
9 * Copyright (C) 1997-2002 Russell king
18 #include "proc-macros.S"
42 ENTRY(fa_flush_icache_all)
51 * Clean and invalidate all cache entries in a particular address
54 ENTRY(fa_flush_user_cache_all)
61 ENTRY(fa_flush_kern_cache_all)
[all …]
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| D | cache-v4wb.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/cache-v4wb.S
5 * Copyright (C) 1997-2002 Russell king
11 #include "proc-macros.S"
38 * 32768 150 149 150 214 216 212 <---
41 * Whole 132 136 132 221 217 207 <---
56 ENTRY(v4wb_flush_icache_all)
65 * Clean and invalidate all cache entries in a particular address
68 ENTRY(v4wb_flush_user_cache_all)
75 ENTRY(v4wb_flush_kern_cache_all)
[all …]
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| D | proc-arm946.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/arm946.S: utility functions for ARM946E-S
5 * Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com)
7 * (Many of cache codes are from proc-arm926.S)
14 #include <asm/pgtable-hwdef.h>
16 #include "proc-macros.S"
19 * ARM946E-S is synthesizable to have 0KB to 1MB sized D-Cache,
35 ENTRY(cpu_arm946_proc_init)
36 ENTRY(cpu_arm946_switch_mm)
42 ENTRY(cpu_arm946_proc_fin)
[all …]
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| D | cache-v4.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/cache-v4.S
5 * Copyright (C) 1997-2002 Russell king
11 #include "proc-macros.S"
18 ENTRY(v4_flush_icache_all)
25 * Invalidate all cache entries in a particular address
28 * - mm - mm_struct describing address space
30 ENTRY(v4_flush_user_cache_all)
37 ENTRY(v4_flush_kern_cache_all)
50 * address space.
[all …]
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| D | cache-v4wt.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/cache-v4wt.S
5 * Copyright (C) 1997-2002 Russell king
15 #include "proc-macros.S"
46 ENTRY(v4wt_flush_icache_all)
55 * Invalidate all cache entries in a particular address
58 ENTRY(v4wt_flush_user_cache_all)
65 ENTRY(v4wt_flush_kern_cache_all)
78 * address space.
80 * - start - start address (inclusive, page aligned)
[all …]
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| D | proc-arm926.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/arch/arm/mm/proc-arm926.S: MMU functions for ARM926EJ-S
5 * Copyright (C) 1999-2001 ARM Limited
7 * hacked for non-paged-MM by Hyok S. Choi, 2003.
12 * CONFIG_CPU_ARM926_CPU_IDLE -> nohlt
19 #include <asm/pgtable-hwdef.h>
22 #include "proc-macros.S"
26 * using the single invalidate entry instructions. Anything larger
43 ENTRY(cpu_arm926_proc_init)
49 ENTRY(cpu_arm926_proc_fin)
[all …]
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| D | proc-arm922.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/arch/arm/mm/proc-arm922.S: MMU functions for ARM922
8 * hacked for non-paged-MM by Hyok S. Choi, 2003.
13 * CONFIG_CPU_ARM922_CPU_IDLE -> nohlt
20 #include <asm/pgtable-hwdef.h>
23 #include "proc-macros.S"
53 ENTRY(cpu_arm922_proc_init)
59 ENTRY(cpu_arm922_proc_fin)
77 ENTRY(cpu_arm922_reset)
96 ENTRY(cpu_arm922_do_idle)
[all …]
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| D | proc-arm925.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 * Copyright (C) 2002-2003 MontaVista Software, Inc.
10 * Update for Linux-2.6 and cache flush improvements
13 * hacked for non-paged-MM by Hyok S. Choi, 2004.
18 * CONFIG_CPU_ARM925_CPU_IDLE -> nohlt
20 * Some additional notes based on deciphering the TI TRM on OMAP-5910:
22 * NOTE1: The TI925T Configuration Register bit "D-cache clean and flush
23 * entry mode" must be 0 to flush the entries in both segments
24 * at once. This is the default value. See TRM 2-20 and 2-24 for
27 * NOTE2: Default is the "D-cache clean and flush entry mode". It looks
[all …]
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| /kernel/linux/linux-5.10/arch/arm/mm/ |
| D | cache-fa.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/cache-fa.S
6 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
8 * Based on cache-v4wb.S:
9 * Copyright (C) 1997-2002 Russell king
19 #include "proc-macros.S"
43 ENTRY(fa_flush_icache_all)
52 * Clean and invalidate all cache entries in a particular address
55 ENTRY(fa_flush_user_cache_all)
62 ENTRY(fa_flush_kern_cache_all)
[all …]
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| D | cache-v4wb.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/cache-v4wb.S
5 * Copyright (C) 1997-2002 Russell king
12 #include "proc-macros.S"
39 * 32768 150 149 150 214 216 212 <---
42 * Whole 132 136 132 221 217 207 <---
57 ENTRY(v4wb_flush_icache_all)
66 * Clean and invalidate all cache entries in a particular address
69 ENTRY(v4wb_flush_user_cache_all)
76 ENTRY(v4wb_flush_kern_cache_all)
[all …]
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| D | proc-arm946.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/arm946.S: utility functions for ARM946E-S
5 * Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com)
7 * (Many of cache codes are from proc-arm926.S)
14 #include <asm/pgtable-hwdef.h>
16 #include "proc-macros.S"
19 * ARM946E-S is synthesizable to have 0KB to 1MB sized D-Cache,
35 ENTRY(cpu_arm946_proc_init)
36 ENTRY(cpu_arm946_switch_mm)
42 ENTRY(cpu_arm946_proc_fin)
[all …]
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| D | cache-v4.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/cache-v4.S
5 * Copyright (C) 1997-2002 Russell king
11 #include "proc-macros.S"
18 ENTRY(v4_flush_icache_all)
25 * Invalidate all cache entries in a particular address
28 * - mm - mm_struct describing address space
30 ENTRY(v4_flush_user_cache_all)
37 ENTRY(v4_flush_kern_cache_all)
50 * address space.
[all …]
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| D | cache-v4wt.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/cache-v4wt.S
5 * Copyright (C) 1997-2002 Russell king
15 #include "proc-macros.S"
46 ENTRY(v4wt_flush_icache_all)
55 * Invalidate all cache entries in a particular address
58 ENTRY(v4wt_flush_user_cache_all)
65 ENTRY(v4wt_flush_kern_cache_all)
78 * address space.
80 * - start - start address (inclusive, page aligned)
[all …]
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| D | proc-arm926.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/arch/arm/mm/proc-arm926.S: MMU functions for ARM926EJ-S
5 * Copyright (C) 1999-2001 ARM Limited
7 * hacked for non-paged-MM by Hyok S. Choi, 2003.
12 * CONFIG_CPU_ARM926_CPU_IDLE -> nohlt
19 #include <asm/pgtable-hwdef.h>
22 #include "proc-macros.S"
26 * using the single invalidate entry instructions. Anything larger
43 ENTRY(cpu_arm926_proc_init)
49 ENTRY(cpu_arm926_proc_fin)
[all …]
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| D | proc-arm922.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/arch/arm/mm/proc-arm922.S: MMU functions for ARM922
8 * hacked for non-paged-MM by Hyok S. Choi, 2003.
13 * CONFIG_CPU_ARM922_CPU_IDLE -> nohlt
20 #include <asm/pgtable-hwdef.h>
23 #include "proc-macros.S"
53 ENTRY(cpu_arm922_proc_init)
59 ENTRY(cpu_arm922_proc_fin)
77 ENTRY(cpu_arm922_reset)
96 ENTRY(cpu_arm922_do_idle)
[all …]
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| D | proc-arm925.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 * Copyright (C) 2002-2003 MontaVista Software, Inc.
10 * Update for Linux-2.6 and cache flush improvements
13 * hacked for non-paged-MM by Hyok S. Choi, 2004.
18 * CONFIG_CPU_ARM925_CPU_IDLE -> nohlt
20 * Some additional notes based on deciphering the TI TRM on OMAP-5910:
22 * NOTE1: The TI925T Configuration Register bit "D-cache clean and flush
23 * entry mode" must be 0 to flush the entries in both segments
24 * at once. This is the default value. See TRM 2-20 and 2-24 for
27 * NOTE2: Default is the "D-cache clean and flush entry mode". It looks
[all …]
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| D | proc-mohawk.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/arch/arm/mm/proc-mohawk.S: MMU functions for Marvell PJ1 core
7 * Heavily based on proc-arm926.S and proc-xsc3.S
15 #include <asm/pgtable-hwdef.h>
18 #include "proc-macros.S"
34 ENTRY(cpu_mohawk_proc_init)
40 ENTRY(cpu_mohawk_proc_fin)
60 ENTRY(cpu_mohawk_reset)
79 ENTRY(cpu_mohawk_do_idle)
90 ENTRY(mohawk_flush_icache_all)
[all …]
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| /kernel/linux/linux-5.10/net/x25/ |
| D | x25_route.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
26 static int x25_add_route(struct x25_address *address, unsigned int sigdigits, in x25_add_route() argument
30 struct list_head *entry; in x25_add_route() local
31 int rc = -EINVAL; in x25_add_route()
35 list_for_each(entry, &x25_route_list) { in x25_add_route()
36 rt = list_entry(entry, struct x25_route, node); in x25_add_route()
38 if (!memcmp(&rt->address, address, sigdigits) && in x25_add_route()
39 rt->sigdigits == sigdigits) in x25_add_route()
44 rc = -ENOMEM; in x25_add_route()
48 strcpy(rt->address.x25_addr, "000000000000000"); in x25_add_route()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/tegra/ |
| D | nvidia,tegra20-host1x.txt | 4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 For pre-Tegra186, one entry describing the whole register area.
7 For Tegra186, one entry for each entry in reg-names:
8 "vm" - VM region assigned to Linux
9 "hypervisor" - Hypervisor region (only if Linux acts as hypervisor)
10 - interrupts: The interrupt outputs from the controller.
11 - #address-cells: The number of cells used to represent physical base addresses
12 in the host1x address space. Should be 1.
13 - #size-cells: The number of cells used to represent the size of an address
[all …]
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