Home
last modified time | relevance | path

Searched +full:ethernet +full:- +full:port (Results 1 – 25 of 1165) sorted by relevance

12345678910>>...47

/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dcortina,gemini-ethernet.txt1 Cortina Systems Gemini Ethernet Controller
4 This ethernet controller is found in the Gemini SoC family:
9 - compatible: must be "cortina,gemini-ethernet"
10 - reg: must contain the global registers and the V-bit and A-bit
12 - syscon: a phandle to the system controller
13 - #address-cells: must be specified, must be <1>
14 - #size-cells: must be specified, must be <1>
15 - ranges: should be state like this giving a 1:1 address translation
18 The subnodes represents the two ethernet ports in this device.
23 - port0: contains the resources for ethernet port 0
[all …]
Dmarvell-orion-net.txt1 Marvell Orion/Discovery ethernet controller
4 The Marvell Discovery ethernet controller can be found on Marvell Orion SoCs
8 The Discovery ethernet controller is described with two levels of nodes. The
9 first level describes the ethernet controller itself and the second level
10 describes up to 3 ethernet port nodes within that controller. The reason for
11 the multiple levels is that the port registers are interleaved within a single
12 set of controller registers. Each port node describes port-specific properties.
16 only one port associated. Multiple ports are implemented as multiple single-port
20 * Ethernet controller node
23 - #address-cells: shall be 1.
[all …]
Dhisilicon-hip04-net.txt1 Hisilicon hip04 Ethernet Controller
3 * Ethernet controller node
6 - compatible: should be "hisilicon,hip04-mac".
7 - reg: address and length of the register set for the device.
8 - interrupts: interrupt for the device.
9 - port-handle: <phandle port channel>
11 port, port number connected to the controller
13 group, field in the pkg desc, in general, it is the same as the port.
14 - phy-mode: see ethernet.txt [1].
17 - phy-handle: see ethernet.txt [1].
[all …]
Dcavium-pip.txt1 * PIP Ethernet nexus.
3 The PIP Ethernet nexus can control several data packet input/output
6 ports might be an individual Ethernet PHY.
10 - compatible: "cavium,octeon-3860-pip"
14 - reg: The base address of the PIP's register bank.
16 - #address-cells: Must be <1>.
18 - #size-cells: Must be <0>.
21 - compatible: "cavium,octeon-3860-pip-interface"
25 - reg: The interface number.
27 - #address-cells: Must be <1>.
[all …]
Dfsl-enetc.txt1 * ENETC ethernet device tree bindings
3 Depending on board design and ENETC port type (internal or
9 - reg : Specifies PCIe Device Number and Function
12 - compatible : Should be "fsl,enetc".
14 1. The ENETC external port is connected to a MDIO configurable phy
16 1.1. Using the local ENETC Port MDIO interface
18 In this case, the ENETC node should include a "mdio" sub-node
19 that in turn should contain the "ethernet-phy" node describing the
21 already defined in Documentation/devicetree/bindings/net/ethernet.txt or
26 - phy-handle : Phandle to a PHY on the MDIO bus.
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/microchip/
Dsparx5_pcb135_board.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 gpio-restart {
11 compatible = "gpio-restart";
17 compatible = "gpio-leds";
21 default-state = "off";
26 default-state = "off";
31 default-state = "off";
36 default-state = "off";
41 default-state = "off";
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Dcortina,gemini-ethernet.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/cortina,gemini-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cortina Systems Gemini Ethernet Controller
10 - Linus Walleij <linus.walleij@linaro.org>
13 This ethernet controller is found in the Gemini SoC family:
19 const: cortina,gemini-ethernet
23 description: must contain the global registers and the V-bit and A-bit
26 "#address-cells":
[all …]
Dmarvell-orion-net.txt1 Marvell Orion/Discovery ethernet controller
4 The Marvell Discovery ethernet controller can be found on Marvell Orion SoCs
8 The Discovery ethernet controller is described with two levels of nodes. The
9 first level describes the ethernet controller itself and the second level
10 describes up to 3 ethernet port nodes within that controller. The reason for
11 the multiple levels is that the port registers are interleaved within a single
12 set of controller registers. Each port node describes port-specific properties.
16 only one port associated. Multiple ports are implemented as multiple single-port
20 * Ethernet controller node
23 - #address-cells: shall be 1.
[all …]
Dhisilicon-hip04-net.txt1 Hisilicon hip04 Ethernet Controller
3 * Ethernet controller node
6 - compatible: should be "hisilicon,hip04-mac".
7 - reg: address and length of the register set for the device.
8 - interrupts: interrupt for the device.
9 - port-handle: <phandle port channel>
11 port, port number connected to the controller
13 group, field in the pkg desc, in general, it is the same as the port.
14 - phy-mode: see ethernet.txt [1].
17 - phy-handle: see ethernet.txt [1].
[all …]
Dethernet-switch.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic Ethernet Switch
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Vladimir Oltean <olteanv@gmail.com>
15 Ethernet switches are multi-port Ethernet controllers. Each port has
16 its own number and is represented as its own Ethernet controller.
[all …]
Dmarvell,pp2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell CN913X / Marvell Armada 375, 7K, 8K Ethernet Controller
10 - Marcin Wojtas <mw@semihalf.com>
11 - Russell King <linux@armlinux.org>
14 Marvell Armada 375 Ethernet Controller (PPv2.1)
15 Marvell Armada 7K/8K Ethernet Controller (PPv2.2)
16 Marvell CN913X Ethernet Controller (PPv2.3)
21 - marvell,armada-375-pp2
[all …]
Dcavium-pip.txt1 * PIP Ethernet nexus.
3 The PIP Ethernet nexus can control several data packet input/output
6 ports might be an individual Ethernet PHY.
10 - compatible: "cavium,octeon-3860-pip"
14 - reg: The base address of the PIP's register bank.
16 - #address-cells: Must be <1>.
18 - #size-cells: Must be <0>.
21 - compatible: "cavium,octeon-3860-pip-interface"
25 - reg: The interface number.
27 - #address-cells: Must be <1>.
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/dsa/
Dmediatek,mt7530.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek MT7530 and MT7531 Ethernet Switches
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Landen Chao <Landen.Chao@mediatek.com>
12 - DENG Qingfang <dqfext@gmail.com>
13 - Sean Wang <sean.wang@mediatek.com>
14 - Daniel Golle <daniel@makrotopia.org>
17 There are three versions of MT7530, standalone, in a multi-chip module and
[all …]
Dqca8k.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - John Crispin <john@phrozen.org>
13 If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
14 describing a port needs to have a valid phandle referencing the internal PHY
15 it is connected to. This is because there is no N:N mapping of port and PHY
16 ID. To declare the internal mdio-bus configuration, declare an MDIO node in
17 the switch node and declare the phandle for the port, referencing the internal
18 PHY it is connected to. In this config, an internal mdio-bus is registered and
[all …]
Dmicrochip,lan937x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LAN937x Ethernet Switch Series
10 - UNGLinuxDriver@microchip.com
13 - $ref: dsa.yaml#/$defs/ethernet-ports
18 - microchip,lan9370
19 - microchip,lan9371
20 - microchip,lan9372
21 - microchip,lan9373
[all …]
Ddsa-port.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/dsa/dsa-port.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic DSA Switch Port
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Vladimir Oltean <olteanv@gmail.com>
15 A DSA switch port is a component of a switch that manages one MAC, and can
16 pass Ethernet frames. It can act as a stanadard Ethernet switch port, or have
[all …]
/kernel/linux/linux-5.10/arch/mips/boot/dts/cavium-octeon/
Docteon_3xxx.dts1 // SPDX-License-Identifier: GPL-2.0
6 * use. Because of this, it contains a super-set of the available
15 phy0: ethernet-phy@0 {
17 marvell,reg-init =
21 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
22 /* irq, blink-activity, blink-link */
23 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
27 phy1: ethernet-phy@1 {
29 marvell,reg-init =
33 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
[all …]
Docteon_68xx.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
7 * use. Because of this, it contains a super-set of the available
11 compatible = "cavium,octeon-6880";
12 #address-cells = <2>;
13 #size-cells = <2>;
14 interrupt-parent = <&ciu2>;
17 compatible = "simple-bus";
18 #address-cells = <2>;
19 #size-cells = <2>;
[all …]
/kernel/linux/linux-6.6/arch/mips/boot/dts/cavium-octeon/
Docteon_3xxx.dts1 // SPDX-License-Identifier: GPL-2.0
6 * use. Because of this, it contains a super-set of the available
15 phy0: ethernet-phy@0 {
17 marvell,reg-init =
21 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
22 /* irq, blink-activity, blink-link */
23 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
27 phy1: ethernet-phy@1 {
29 marvell,reg-init =
33 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
[all …]
Docteon_68xx.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
7 * use. Because of this, it contains a super-set of the available
11 compatible = "cavium,octeon-6880";
12 #address-cells = <2>;
13 #size-cells = <2>;
14 interrupt-parent = <&ciu2>;
17 compatible = "simple-bus";
18 #address-cells = <2>;
19 #size-cells = <2>;
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/
Dfsl-lx2160a-bluebox3.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 // Copyright 2020-2021 NXP
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2160a-bluebox3", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "MC34717-3.3VSB";
29 regulator-min-microvolt = <3300000>;
[all …]
/kernel/linux/linux-5.10/Documentation/networking/dsa/
Ddsa.rst14 to support Marvell Ethernet switches (MV88E6xxx, a.k.a Linkstreet product line)
19 they configured/queried a switch port network device or a regular network
22 An Ethernet switch is typically comprised of multiple front-panel ports, and one
23 or more CPU or management port. The DSA subsystem currently relies on the
24 presence of a management port connected to an Ethernet controller capable of
25 receiving Ethernet frames from the switch. This is a very common setup for all
26 kinds of Ethernet switches found in Small Home and Office products: routers,
27 gateways, or even top-of-the rack switches. This host Ethernet controller will
32 using upstream and downstream Ethernet links between switches. These specific
36 For each front-panel port, DSA will create specialized network devices which are
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/dsa/
Ddsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ethernet Switch Device Tree Bindings
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Vivien Didelot <vivien.didelot@gmail.com>
15 This binding represents Ethernet Switches which have a dedicated CPU
16 port. That port is usually connected to an Ethernet Controller of the
32 (single device hanging off a CPU port) must not specify this property
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/marvell/
Dorion5x-netgear-wnr854t.dts1 // SPDX-License-Identifier: GPL-2.0-only
4 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include "orion5x-mv88f5181.dtsi"
11 model = "Netgear WNR854-t";
12 compatible = "netgear,wnr854t", "marvell,orion5x-88f5181",
24 stdout-path = "serial0:115200n8";
33 gpio-keys {
34 compatible = "gpio-keys";
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dorion5x-netgear-wnr854t.dts9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include "orion5x-mv88f5181.dtsi"
16 model = "Netgear WNR854-t";
17 compatible = "netgear,wnr854t", "marvell,orion5x-88f5181",
29 stdout-path = "serial0:115200n8";
38 gpio-keys {
39 compatible = "gpio-keys";
40 pinctrl-0 = <&pmx_reset_button>;
[all …]

12345678910>>...47