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/kernel/linux/linux-5.10/sound/soc/pxa/
Dz2.c1 // SPDX-License-Identifier: GPL-2.0-only
23 #include <asm/mach-types.h>
29 #include "pxa2xx-i2s.h"
39 unsigned int clk = 0; in z2_hw_params() local
47 clk = 12288000; in z2_hw_params()
52 clk = 11289600; in z2_hw_params()
57 ret = snd_soc_dai_set_sysclk(codec_dai, WM8750_SYSCLK, clk, in z2_hw_params()
76 .pin = "Mic Jack",
80 .pin = "Headphone Jack",
84 .pin = "Ext Spk",
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/iio/imu/
Dadi,adis16480.txt6 - compatible: Must be one of
12 * "adi,adis16495-1"
13 * "adi,adis16495-2"
14 * "adi,adis16495-3"
15 * "adi,adis16497-1"
16 * "adi,adis16497-2"
17 * "adi,adis16497-3"
18 - reg: SPI chip select number for the device
19 - spi-max-frequency: Max SPI frequency to use
20 see: Documentation/devicetree/bindings/spi/spi-bus.txt
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/rtc/
Drtc-omap.txt4 - compatible:
5 - "ti,da830-rtc" - for RTC IP used similar to that on DA8xx SoC family.
6 - "ti,am3352-rtc" - for RTC IP used similar to that on AM335x SoC family.
7 This RTC IP has special WAKE-EN Register to enable
10 pmic_power_en pin.
11 - "ti,am4372-rtc" - for RTC IP used similar to that on AM437X SoC family.
12 - reg: Address range of rtc register set
13 - interrupts: rtc timer, alarm interrupts in order
16 - system-power-controller: whether the rtc is controlling the system power
18 - clocks: Any internal or external clocks feeding in to rtc
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/rtc/
Drtc-omap.txt4 - compatible:
5 - "ti,da830-rtc" - for RTC IP used similar to that on DA8xx SoC family.
6 - "ti,am3352-rtc" - for RTC IP used similar to that on AM335x SoC family.
7 This RTC IP has special WAKE-EN Register to enable
10 pmic_power_en pin.
11 - "ti,am4372-rtc" - for RTC IP used similar to that on AM437X SoC family.
12 - reg: Address range of rtc register set
13 - interrupts: rtc timer, alarm interrupts in order
16 - system-power-controller: whether the rtc is controlling the system power
18 - clocks: Any internal or external clocks feeding in to rtc
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/iio/imu/
Dadi,adis16480.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandru Tachici <alexandru.tachici@analog.com>
15 - adi,adis16375
16 - adi,adis16480
17 - adi,adis16485
18 - adi,adis16488
19 - adi,adis16490
20 - adi,adis16495-1
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Ds5pv210-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
19 #include <dt-bindings/pinctrl/samsung.h>
24 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \
25 samsung,pin-pud-pdn = <S3C64XX_PIN_PULL_ ##_pull>; \
30 gpio-controller;
31 #gpio-cells = <2>;
33 interrupt-controller;
34 #interrupt-cells = <2>;
38 gpio-controller;
[all …]
Dexynos4210-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source
5 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2011-2012 Linaro Ltd.
10 * Samsung's Exynos4210 SoC pin-mux and pin-config optiosn are listed as device
14 #include <dt-bindings/pinctrl/samsung.h>
18 gpio-controller;
19 #gpio-cells = <2>;
21 interrupt-controller;
22 #interrupt-cells = <2>;
[all …]
Dexynos4412-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4412 SoCs pin-mux and pin-config device tree source
8 * Samsung's Exynos4412 SoCs pin-mux and pin-config optiosn are listed as device
12 #include <dt-bindings/pinctrl/samsung.h>
17 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \
18 samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_ ##_pull>; \
23 gpio-controller;
24 #gpio-cells = <2>;
26 interrupt-controller;
27 #interrupt-cells = <2>;
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/samsung/
Dexynos4x12-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source
8 * Samsung's Exynos4x12 SoCs pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 pin- ## _pin { \
17 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \
18 samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_ ##_pull>; \
22 gpa0: gpa0-gpio-bank {
23 gpio-controller;
24 #gpio-cells = <2>;
[all …]
Ds5pv210-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's S5PV210 SoC device tree source - pin control-related
6 * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
11 * Samsung's S5PV210 SoC pin banks, pin-mux and pin-config options are
15 #include "s5pv210-pinctrl.h"
18 pin- ## _pin { \
20 samsung,pin-con-pdn = <S5PV210_PIN_PDN_ ##_mode>; \
21 samsung,pin-pud-pdn = <S5PV210_PIN_PULL_ ##_pull>; \
25 gpa0: gpa0-gpio-bank {
26 gpio-controller;
[all …]
Dexynos4210-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source
5 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2011-2012 Linaro Ltd.
10 * Samsung's Exynos4210 SoC pin-mux and pin-config options are listed as device
14 #include "exynos-pinctrl.h"
17 gpa0: gpa0-gpio-bank {
18 gpio-controller;
19 #gpio-cells = <2>;
21 interrupt-controller;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/qcom/
Dmsm8916-pins.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
8 blsp1_uart1_default: blsp1-uart1-default {
13 drive-strength = <16>;
14 bias-disable;
17 blsp1_uart1_sleep: blsp1-uart1-sleep {
21 drive-strength = <2>;
22 bias-pull-down;
25 blsp1_uart2_default: blsp1-uart2-default {
29 drive-strength = <16>;
[all …]
/kernel/linux/linux-5.10/drivers/pinctrl/
Dpinctrl-u300.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for the U300 pin controller
6 * Copyright (C) 2009-2011 ST-Ericsson AB
25 #include <linux/pinctrl/pinconf-generic.h>
26 #include "pinctrl-coh901.h"
170 #define DRIVER_NAME "pinctrl-u300"
258 PINCTRL_PIN(69, "PO RF CTRL CLK"),
265 PINCTRL_PIN(76, "PI M CLK"),
266 PINCTRL_PIN(77, "PI RTC CLK"),
271 PINCTRL_PIN(82, "PO SYS 1 CLK"),
[all …]
/kernel/linux/linux-6.6/sound/soc/intel/boards/
Dcml_rt1011_rt5682.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk.h>
21 #include <sound/soc-acpi.h>
29 #define CML_RT1011_CODEC_DAI "rt1011-aif"
30 #define CML_RT5682_CODEC_DAI "rt5682-aif1"
44 sof_rt1011_quirk = (unsigned long)id->driver_data; in sof_rt1011_quirk_cb()
80 SOC_DAPM_PIN_SWITCH("WL Ext Spk"),
81 SOC_DAPM_PIN_SWITCH("WR Ext Spk"),
85 SOC_DAPM_PIN_SWITCH("TL Ext Spk"),
86 SOC_DAPM_PIN_SWITCH("TR Ext Spk"),
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/
Dimx8mq-nitrogen.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/input/input.h>
13 compatible = "boundary,imx8mq-nitrogen8m", "fsl,imx8mq";
16 stdout-path = "serial0:115200n8";
24 gpio-keys {
25 compatible = "gpio-keys";
26 pinctrl-names = "default";
27 pinctrl-0 = <&pinctrl_gpio_keys>;
33 wakeup-source;
[all …]
/kernel/linux/linux-5.10/sound/soc/intel/boards/
Dcml_rt1011_rt5682.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk.h>
21 #include <sound/soc-acpi.h>
29 #define CML_RT1011_CODEC_DAI "rt1011-aif"
30 #define CML_RT5682_CODEC_DAI "rt5682-aif1"
44 sof_rt1011_quirk = (unsigned long)id->driver_data; in sof_rt1011_quirk_cb()
80 SOC_DAPM_PIN_SWITCH("WL Ext Spk"),
81 SOC_DAPM_PIN_SWITCH("WR Ext Spk"),
85 SOC_DAPM_PIN_SWITCH("TL Ext Spk"),
86 SOC_DAPM_PIN_SWITCH("TR Ext Spk"),
[all …]
Dcht_bsw_rt5672.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * cht_bsw_rt5672.c - ASoc Machine driver for Intel Cherryview-based platforms
16 #include <linux/clk.h>
21 #include <sound/soc-acpi.h>
23 #include "../atom/sst-atom-controls.h"
28 #define CHT_CODEC_DAI "rt5670-aif1"
33 struct clk *mclk;
39 .pin = "Headset Mic",
43 .pin = "Headphone",
51 struct snd_soc_dapm_context *dapm = w->dapm; in platform_clock_control()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dsti-dwmac.txt10 - compatible : Can be "st,stih415-dwmac", "st,stih416-dwmac",
11 "st,stih407-dwmac", "st,stid127-dwmac".
12 - st,syscon : Should be phandle/offset pair. The phandle to the syscon node which
14 - st,gmac_en: this is to enable the gmac into a dedicated sysctl control
16 - pinctrl-0: pin-control for all the MII mode supported.
19 - resets : phandle pointing to the system reset controller with correct
21 - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or
23 - st,tx-retime-src: This specifies which clk is wired up to the mac for
27 - sti-ethclk: this is the phy clock.
28 - sti-clkconf: this is an extra sysconfig register, available in new SoCs,
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Dsti-dwmac.txt10 - compatible : "st,stih407-dwmac"
11 - st,syscon : Should be phandle/offset pair. The phandle to the syscon node which
13 - st,gmac_en: this is to enable the gmac into a dedicated sysctl control
15 - pinctrl-0: pin-control for all the MII mode supported.
18 - resets : phandle pointing to the system reset controller with correct
20 - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or
22 - st,tx-retime-src: This specifies which clk is wired up to the mac for
26 - sti-ethclk: this is the phy clock.
27 - sti-clkconf: this is an extra sysconfig register, available in new SoCs,
28 to program the clk retiming.
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/iio/adc/
Dadi,ad4130.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Cosmin Tanislav <cosmin.tanislav@analog.com>
15 https://www.analog.com/media/en/technical-documentation/data-sheets/AD4130-8.pdf
20 - adi,ad4130
29 clock-names:
31 - const: mclk
36 interrupt-names:
38 Specify which interrupt pin should be configured as Data Ready / FIFO
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/
Dimx8mq-nitrogen.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/input/input.h>
13 compatible = "boundary,imx8mq-nitrogen8m", "fsl,imx8mq";
16 stdout-path = "serial0:115200n8";
24 gpio-keys {
25 compatible = "gpio-keys";
26 pinctrl-names = "default";
27 pinctrl-0 = <&pinctrl_gpio_keys>;
29 button-power {
[all …]
/kernel/linux/linux-6.6/drivers/clk/
Dclk-palmas.c1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (c) 2013-2014 Texas Instruments, Inc.
12 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
57 ret = palmas_update_bits(cinfo->palmas, PALMAS_RESOURCE_BASE, in palmas_clks_prepare()
58 cinfo->clk_desc->control_reg, in palmas_clks_prepare()
59 cinfo->clk_desc->enable_mask, in palmas_clks_prepare()
60 cinfo->clk_desc->enable_mask); in palmas_clks_prepare()
62 dev_err(cinfo->dev, "Reg 0x%02x update failed, %d\n", in palmas_clks_prepare()
63 cinfo->clk_desc->control_reg, ret); in palmas_clks_prepare()
[all …]
/kernel/linux/linux-5.10/drivers/clk/
Dclk-palmas.c5 * Copyright (c) 2013-2014 Texas Instruments, Inc.
20 #include <linux/clk.h>
21 #include <linux/clk-provider.h>
66 ret = palmas_update_bits(cinfo->palmas, PALMAS_RESOURCE_BASE, in palmas_clks_prepare()
67 cinfo->clk_desc->control_reg, in palmas_clks_prepare()
68 cinfo->clk_desc->enable_mask, in palmas_clks_prepare()
69 cinfo->clk_desc->enable_mask); in palmas_clks_prepare()
71 dev_err(cinfo->dev, "Reg 0x%02x update failed, %d\n", in palmas_clks_prepare()
72 cinfo->clk_desc->control_reg, ret); in palmas_clks_prepare()
73 else if (cinfo->clk_desc->delay) in palmas_clks_prepare()
[all …]
/kernel/linux/linux-5.10/arch/sh/include/cpu-sh4/cpu/
Dsh7785.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 * MODE0: CPG - Initial Pck/Bck Frequency [FRQMR1]
8 * MODE1: CPG - Initial Uck/SHck/DDRck Frequency [FRQMR1]
9 * MODE2: CPG - Reserved (L: Normal operation)
10 * MODE3: CPG - Reserved (L: Normal operation)
11 * MODE4: CPG - Initial PLL setting (72x/36x)
12 * MODE5: LBSC - Area0 Memory Type / Bus Width [CS0BCR.8]
13 * MODE6: LBSC - Area0 Memory Type / Bus Width [CS0BCR.9]
14 * MODE7: LBSC - Area0 Memory Type / Bus Width [CS0BCR.3]
15 * MODE8: LBSC - Endian Mode (L: Big, H: Little) [BCR.31]
[all …]
/kernel/linux/linux-6.6/arch/sh/include/cpu-sh4/cpu/
Dsh7785.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 * MODE0: CPG - Initial Pck/Bck Frequency [FRQMR1]
8 * MODE1: CPG - Initial Uck/SHck/DDRck Frequency [FRQMR1]
9 * MODE2: CPG - Reserved (L: Normal operation)
10 * MODE3: CPG - Reserved (L: Normal operation)
11 * MODE4: CPG - Initial PLL setting (72x/36x)
12 * MODE5: LBSC - Area0 Memory Type / Bus Width [CS0BCR.8]
13 * MODE6: LBSC - Area0 Memory Type / Bus Width [CS0BCR.9]
14 * MODE7: LBSC - Area0 Memory Type / Bus Width [CS0BCR.3]
15 * MODE8: LBSC - Endian Mode (L: Big, H: Little) [BCR.31]
[all …]

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