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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dingenic,cgu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The CGU in an Ingenic SoC provides all the clocks generated on-chip. It
16 - Paul Cercueil <paul@crapouillou.net>
23 - ingenic,jz4740-cgu
24 - ingenic,jz4725b-cgu
25 - ingenic,jz4755-cgu
26 - ingenic,jz4760-cgu
27 - ingenic,jz4760b-cgu
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Dcpsw-phy-sel.txt1 TI CPSW Phy mode Selection Device Tree Bindings (DEPRECATED)
2 -----------------------------------------------
5 - compatible : Should be "ti,am3352-cpsw-phy-sel" for am335x platform and
6 "ti,dra7xx-cpsw-phy-sel" for dra7xx platform
7 "ti,am43xx-cpsw-phy-sel" for am43xx platform
8 - reg : physical base address and size of the cpsw
10 - reg-names : names of the register map given in "reg" node
13 -rmii-clock-ext : If present, the driver will configure the RMII
18 phy_sel: cpsw-phy-sel@44e10650 {
19 compatible = "ti,am3352-cpsw-phy-sel";
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dcpsw-phy-sel.txt1 TI CPSW Phy mode Selection Device Tree Bindings (DEPRECATED)
2 -----------------------------------------------
5 - compatible : Should be "ti,am3352-cpsw-phy-sel" for am335x platform and
6 "ti,dra7xx-cpsw-phy-sel" for dra7xx platform
7 "ti,am43xx-cpsw-phy-sel" for am43xx platform
8 - reg : physical base address and size of the cpsw
10 - reg-names : names of the register map given in "reg" node
13 -rmii-clock-ext : If present, the driver will configure the RMII
18 phy_sel: cpsw-phy-sel@44e10650 {
19 compatible = "ti,am3352-cpsw-phy-sel";
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dingenic,cgu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The CGU in an Ingenic SoC provides all the clocks generated on-chip. It
16 - Paul Cercueil <paul@crapouillou.net>
23 - ingenic,jz4740-cgu
24 - ingenic,jz4725b-cgu
25 - ingenic,jz4770-cgu
26 - ingenic,jz4780-cgu
27 - ingenic,x1000-cgu
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dsocionext,uniphier-usb3ss-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3ss-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 Super-Speed (SS) PHY
10 This describes the devicetree bindings for PHY interfaces built into
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about Super-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro4-usb3-ssphy
[all …]
Dsocionext,uniphier-usb3hs-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 High-Speed (HS) PHY
10 This describes the devicetree bindings for PHY interfaces built into
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about High-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro5-usb3-hsphy
[all …]
Dphy-miphy28lp.txt1 STMicroelectronics STi MIPHY28LP PHY binding
4 This binding describes a miphy device that is used to control PHY hardware
8 - compatible : Should be "st,miphy28lp-phy".
9 - st,syscfg : Should be a phandle of the system configuration register group
12 Required nodes : A sub-node is required for each channel the controller
14 'reg' and 'reg-names' properties are used inside these
19 - #phy-cells : Should be 1 (See second example)
21 - PHY_TYPE_SATA
22 - PHY_TYPE_PCI
23 - PHY_TYPE_USB3
[all …]
/kernel/linux/linux-6.6/drivers/net/phy/
Dsfp.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/mdio/mdio-i2c.h>
13 #include <linux/phy.h>
150 "mod-def0",
152 "tx-fault",
153 "tx-disable",
154 "rate-select0",
155 "rate-select1",
167 /* t_start_up (SFF-8431) or t_init (SFF-8472) is the time required for a
168 * non-cooled module to initialise its laser safety circuitry. We wait
[all …]
/kernel/linux/linux-5.10/drivers/net/phy/
Dsfp.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/mdio/mdio-i2c.h>
14 #include <linux/phy.h>
147 "mod-def0",
149 "tx-fault",
150 "tx-disable",
151 "rate-select0",
162 /* t_start_up (SFF-8431) or t_init (SFF-8472) is the time required for a
163 * non-cooled module to initialise its laser safety circuitry. We wait
164 * an initial T_WAIT period before we check the tx fault to give any PHY
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/nxp/imx/
Dimx6ul-14x14-evk.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/media/video-interfaces.h>
9 stdout-path = &uart1;
17 backlight_display: backlight-display {
18 compatible = "pwm-backlight";
20 brightness-levels = <0 4 8 16 32 64 128 255>;
21 default-brightness-level = <6>;
26 reg_sd1_vmmc: regulator-sd1-vmmc {
27 compatible = "regulator-fixed";
28 regulator-name = "VSD_3V3";
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/
Dphy-miphy28lp.txt1 STMicroelectronics STi MIPHY28LP PHY binding
4 This binding describes a miphy device that is used to control PHY hardware
8 - compatible : Should be "st,miphy28lp-phy".
9 - st,syscfg : Should be a phandle of the system configuration register group
12 Required nodes : A sub-node is required for each channel the controller
14 'reg' and 'reg-names' properties are used inside these
19 - #phy-cells : Should be 1 (See second example)
21 - PHY_TYPE_SATA
22 - PHY_TYPE_PCI
23 - PHY_TYPE_USB3
[all …]
/kernel/linux/linux-5.10/arch/mips/boot/dts/xilfpga/
Dnexys4ddr.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
14 stdout-path = "serial0:115200n8";
22 cpuintc: interrupt-controller {
23 #address-cells = <0>;
24 #interrupt-cells = <1>;
25 interrupt-controller;
26 compatible = "mti,cpu-interrupt-controller";
29 axi_intc: interrupt-controller@10200000 {
30 #interrupt-cells = <1>;
[all …]
/kernel/linux/linux-6.6/arch/mips/boot/dts/xilfpga/
Dnexys4ddr.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
14 stdout-path = "serial0:115200n8";
22 cpuintc: interrupt-controller {
23 #address-cells = <0>;
24 #interrupt-cells = <1>;
25 interrupt-controller;
26 compatible = "mti,cpu-interrupt-controller";
29 axi_intc: interrupt-controller@10200000 {
30 #interrupt-cells = <1>;
[all …]
/kernel/linux/linux-6.6/arch/mips/boot/dts/ingenic/
Djz4780.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
3 #include <dt-bindings/clock/ingenic,tcu.h>
4 #include <dt-bindings/dma/jz4780-dma.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
21 clock-names = "cpu";
[all …]
Djz4770.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,jz4770-cgu.h>
3 #include <dt-bindings/clock/ingenic,tcu.h>
6 #address-cells = <1>;
7 #size-cells = <1>;
11 #address-cells = <1>;
12 #size-cells = <0>;
16 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
20 clock-names = "cpu";
24 cpuintc: interrupt-controller {
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/nxp/ls/
Dls1021a-iot.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2021-2022 NXP
7 /dts-v1/;
11 model = "LS1021A-IOT Board";
12 compatible = "fsl,ls1021a-iot", "fsl,ls1021a";
14 sys_mclk: clock-mclk {
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-frequency = <24576000>;
20 reg_3p3v: regulator-3V3 {
[all …]
Dls1021a-twr.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
7 /dts-v1/;
12 compatible = "fsl,ls1021a-twr", "fsl,ls1021a";
20 sys_mclk: clock-mclk {
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <24576000>;
27 compatible = "regulator-fixed";
28 regulator-name = "3P3V";
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-stm32.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * dwmac-stm32.c - DWMAC Specific Glue layer for STM32 MCU
15 #include <linux/phy.h>
31 /* CLOCK feed to PHY*/
36 /* Ethernet PHY interface selection in register SYSCFG Configuration
37 *------------------------------------------
39 *------------------------------------------
41 *------------------------------------------
43 *------------------------------------------
45 *------------------------------------------
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-stm32.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * dwmac-stm32.c - DWMAC Specific Glue layer for STM32 MCU
16 #include <linux/phy.h>
32 /* CLOCK feed to PHY*/
37 /* Ethernet PHY interface selection in register SYSCFG Configuration
38 *------------------------------------------
40 *------------------------------------------
42 *------------------------------------------
44 *------------------------------------------
46 *------------------------------------------
[all …]
/kernel/linux/linux-5.10/arch/mips/boot/dts/ingenic/
Djz4770.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/jz4770-cgu.h>
3 #include <dt-bindings/clock/ingenic,tcu.h>
6 #address-cells = <1>;
7 #size-cells = <1>;
11 #address-cells = <1>;
12 #size-cells = <0>;
16 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
20 clock-names = "cpu";
24 cpuintc: interrupt-controller {
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/
Dfsl-ls1028a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
12 #include "fsl-ls1028a.dtsi"
16 compatible = "fsl,ls1028a-rdb", "fsl,ls1028a";
25 stdout-path = "serial0:115200n8";
33 sys_mclk: clock-mclk {
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <25000000>;
39 reg_1p8v: regulator-1p8v {
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/atheros/atl1c/
Datl1c_hw.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
37 * 00-0B-6A-F6-00-DC in atl1c_hw_set_mac_addr()
78 /* MAC-address from BIOS is the 1st priority */ in atl1c_get_permanent_address()
79 if (atl1c_read_current_addr(hw, hw->perm_mac_addr)) in atl1c_get_permanent_address()
85 if (hw->nic_type == athr_l1c || hw->nic_type == athr_l2c) { in atl1c_get_permanent_address()
95 if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l2c_b2) { in atl1c_get_permanent_address()
116 return -1; in atl1c_get_permanent_address()
119 if ((hw->nic_type == athr_l1c || hw->nic_type == athr_l2c)) { in atl1c_get_permanent_address()
134 if (atl1c_read_current_addr(hw, hw->perm_mac_addr)) in atl1c_get_permanent_address()
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/atheros/atl1c/
Datl1c_hw.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
37 * 00-0B-6A-F6-00-DC in atl1c_hw_set_mac_addr()
78 /* MAC-address from BIOS is the 1st priority */ in atl1c_get_permanent_address()
79 if (atl1c_read_current_addr(hw, hw->perm_mac_addr)) in atl1c_get_permanent_address()
85 if (hw->nic_type == athr_l1c || hw->nic_type == athr_l2c) { in atl1c_get_permanent_address()
95 if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l2c_b2) { in atl1c_get_permanent_address()
116 return -1; in atl1c_get_permanent_address()
119 if ((hw->nic_type == athr_l1c || hw->nic_type == athr_l2c)) { in atl1c_get_permanent_address()
134 if (atl1c_read_current_addr(hw, hw->perm_mac_addr)) in atl1c_get_permanent_address()
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/intel/iwlwifi/fw/api/
Drx.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2022 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2015-2017 Intel Deutschland GmbH
10 /* API for pre-9000 hardware */
26 * struct iwl_rx_phy_info - phy info
28 * @non_cfg_phy_cnt: non configurable DSP phy data byte count
29 * @cfg_phy_cnt: configurable DSP phy data byte count
30 * @stat_id: configurable DSP phy data set ID
34 * @beacon_time_stamp: beacon at on-air rise
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/
Dqcom,pcie.txt3 - compatible:
7 - "qcom,pcie-ipq8064" for ipq8064
8 - "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065
9 - "qcom,pcie-apq8064" for apq8064
10 - "qcom,pcie-apq8084" for apq8084
11 - "qcom,pcie-msm8996" for msm8996 or apq8096
12 - "qcom,pcie-ipq4019" for ipq4019
13 - "qcom,pcie-ipq8074" for ipq8074
14 - "qcom,pcie-qcs404" for qcs404
15 - "qcom,pcie-sdm845" for sdm845
[all …]

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