Searched +full:external +full:- +full:control (Results 1 – 25 of 1104) sorted by relevance
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | clk-palmas-clk32kg-clocks.txt | 5 This binding uses the common clock binding ./clock-bindings.txt.
8 - compatible : "ti,palmas-clk32kg" for clk32kg clock
9 "ti,palmas-clk32kgaudio" for clk32kgaudio clock
10 - #clock-cells : shall be set to 0.
13 - ti,external-sleep-control: The external enable input pins controlled the
14 enable/disable of clocks. The external enable input pins ENABLE1,
15 ENABLE2 and NSLEEP. The valid values for the external pins are:
20 via register access and these pins do not have any control.
21 The macros of external control pins for DTS is defined at
22 dt-bindings/mfd/palmas.h
[all …]
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| D | pistachio-clock.txt | 5 general control, and top general control) which are instantiated individually
6 from the device-tree.
8 External clocks:
9 ----------------
11 There are three external inputs to the clock controllers which should be
12 defined with the following clock-output-names:
13 - "xtal": External 52Mhz oscillator (required)
14 - "audio_clk_in": Alternate audio reference clock (optional)
15 - "enet_clk_in": Alternate ethernet PHY clock (optional)
18 ----------------------
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | clk-palmas-clk32kg-clocks.txt | 5 This binding uses the common clock binding ./clock-bindings.txt.
8 - compatible : "ti,palmas-clk32kg" for clk32kg clock
9 "ti,palmas-clk32kgaudio" for clk32kgaudio clock
10 - #clock-cells : shall be set to 0.
13 - ti,external-sleep-control: The external enable input pins controlled the
14 enable/disable of clocks. The external enable input pins ENABLE1,
15 ENABLE2 and NSLEEP. The valid values for the external pins are:
20 via register access and these pins do not have any control.
21 The macros of external control pins for DTS is defined at
22 dt-bindings/mfd/palmas.h
[all …]
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| D | pistachio-clock.txt | 5 general control, and top general control) which are instantiated individually
6 from the device-tree.
8 External clocks:
9 ----------------
11 There are three external inputs to the clock controllers which should be
12 defined with the following clock-output-names:
13 - "xtal": External 52Mhz oscillator (required)
14 - "audio_clk_in": Alternate audio reference clock (optional)
15 - "enet_clk_in": Alternate ethernet PHY clock (optional)
18 ----------------------
[all …]
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| /kernel/linux/linux-5.10/drivers/pinctrl/samsung/ |
| D | pinctrl-samsung.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
25 * enum pincfg_type - possible pin configuration types supported.
46 * packed together into a 16-bits. The upper 8-bits represent the configuration
47 * type and the lower 8-bits hold the value of the configuration type.
57 * enum eint_type - possible external interrupt types.
58 * @EINT_TYPE_NONE: bank does not support external interrupts
59 * @EINT_TYPE_GPIO: bank supportes external gpio interrupts
60 * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts
61 * @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts
[all …]
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| /kernel/linux/linux-6.6/drivers/pinctrl/samsung/ |
| D | pinctrl-samsung.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
25 * enum pincfg_type - possible pin configuration types supported.
46 * packed together into a 16-bits. The upper 8-bits represent the configuration
47 * type and the lower 8-bits hold the value of the configuration type.
65 * enum eint_type - possible external interrupt types.
66 * @EINT_TYPE_NONE: bank does not support external interrupts
67 * @EINT_TYPE_GPIO: bank supportes external gpio interrupts
68 * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts
69 * @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts
[all …]
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| /kernel/linux/linux-5.10/arch/m68k/include/asm/ |
| D | MC68328.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68328.h: '328 control registers
8 * Based on include/asm-m68knommu/MC68332.h
26 * 0xFFFFF0xx -- System Control
31 * System Control Register (SCR)
36 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
39 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
42 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
52 * 0xFFFFF1xx -- Chip-Select logic
58 * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
[all …]
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| /kernel/linux/linux-6.6/arch/m68k/include/asm/ |
| D | MC68328.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68328.h: '328 control registers
8 * Based on include/asm-m68knommu/MC68332.h
26 * 0xFFFFF0xx -- System Control
31 * System Control Register (SCR)
36 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
39 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
42 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
52 * 0xFFFFF1xx -- Chip-Select logic
58 * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/regulator/ |
| D | lp872x.txt | 4 - compatible: "ti,lp8720" or "ti,lp8725"
5 - reg: I2C slave address. 0x7d = LP8720, 0x7a = LP8725
8 - ti,general-config: the value of LP872X_GENERAL_CFG register (u8)
10 bit[2]: BUCK output voltage control by external DVS pin or register
11 1 = external pin, 0 = bit7 of register 08h
12 bit[1]: sleep control by external DVS pin or register
13 1 = external pin, 0 = bit6 of register 08h
18 bit[4]: BUCK2 enable control. 1 = enable, 0 = disable
20 bit[2]: BUCK1 output voltage control by external DVS pin or register
22 bit[1]: LDO sleep control. 1 = sleep mode, 0 = normal
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/regulator/ |
| D | lp872x.txt | 4 - compatible: "ti,lp8720" or "ti,lp8725"
5 - reg: I2C slave address. 0x7d = LP8720, 0x7a = LP8725
8 - ti,general-config: the value of LP872X_GENERAL_CFG register (u8)
10 bit[2]: BUCK output voltage control by external DVS pin or register
11 1 = external pin, 0 = bit7 of register 08h
12 bit[1]: sleep control by external DVS pin or register
13 1 = external pin, 0 = bit6 of register 08h
18 bit[4]: BUCK2 enable control. 1 = enable, 0 = disable
20 bit[2]: BUCK1 output voltage control by external DVS pin or register
22 bit[1]: LDO sleep control. 1 = sleep mode, 0 = normal
[all …]
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| /kernel/linux/linux-5.10/arch/powerpc/sysdev/ |
| D | fsl_85xx_cache_ctlr.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright 2009-2010, 2012 Freescale Semiconductor, Inc
38 u32 ctl; /* 0x000 - L2 control */
40 u32 ewar0; /* 0x010 - External write address 0 */
41 u32 ewarea0; /* 0x014 - External write address extended 0 */
42 u32 ewcr0; /* 0x018 - External write ctrl */
44 u32 ewar1; /* 0x020 - External write address 1 */
45 u32 ewarea1; /* 0x024 - External write address extended 1 */
46 u32 ewcr1; /* 0x028 - External write ctrl 1 */
48 u32 ewar2; /* 0x030 - External write address 2 */
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/mfd/ |
| D | as3722.txt | 4 -------------------
5 - compatible: Must be "ams,as3722".
6 - reg: I2C device address.
7 - interrupt-controller: AS3722 has internal interrupt controller which takes the
8 interrupt request from internal sub-blocks like RTC, regulators, GPIOs as well
9 as external input.
10 - #interrupt-cells: Should be set to 2 for IRQ number and flags.
12 of AS3722 are defined at dt-bindings/mfd/as3722.h
14 interrupts.txt, using dt-bindings/irq.
17 --------------------
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| D | stericsson,ab8500.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson Analog Baseband AB8500 and AB8505
10 - Linus Walleij <linus.walleij@linaro.org>
13 the AB8500 "Analog Baseband" is the mixed-signals integrated circuit
14 handling power management (regulators), analog-to-digital conversion
15 (ADC), battery charging, fuel gauging of the battery, battery-backed
16 RTC, PWM, USB PHY and some GPIO lines in the ST-Ericsson U8500 platforms
21 USB charging handling has changed, and it has an embedded USB-to-serial
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mfd/ |
| D | as3722.txt | 4 -------------------
5 - compatible: Must be "ams,as3722".
6 - reg: I2C device address.
7 - interrupt-controller: AS3722 has internal interrupt controller which takes the
8 interrupt request from internal sub-blocks like RTC, regulators, GPIOs as well
9 as external input.
10 - #interrupt-cells: Should be set to 2 for IRQ number and flags.
12 of AS3722 are defined at dt-bindings/mfd/as3722.h
14 interrupts.txt, using dt-bindings/irq.
17 --------------------
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/ |
| D | ti-phy.txt | 3 OMAP CONTROL PHY
6 - compatible: Should be one of
7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
8 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
12 "ti,control-phy-pcie" - for pcie to support external clock for pcie and to
15 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
17 "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
19 - reg : register ranges as listed in the reg-names property
20 - reg-names: "otghs_control" for control-phy-otghs
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | ti-phy.txt | 3 OMAP CONTROL PHY
6 - compatible: Should be one of
7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
8 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
12 "ti,control-phy-pcie" - for pcie to support external clock for pcie and to
15 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
17 "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
19 - reg : register ranges as listed in the reg-names property
20 - reg-names: "otghs_control" for control-phy-otghs
[all …]
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| /kernel/linux/linux-6.6/drivers/memory/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
42 Used to configure the EBI (external bus interface) when the device-
43 tree is used. This bus supports NANDs, external ethernet controller,
64 controller and specifically control the Self Refresh Power Down
68 bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
72 Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU
73 resides Coherency Manager v2 with embedded 1MB L2-cache. It's
75 tags and way-select latencies of RAM access. This driver provides a
76 dt properties-based and sysfs interface for it.
84 SoCs. AEMIF stands for Asynchronous External Memory Interface and
[all …]
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| /kernel/linux/linux-5.10/arch/powerpc/include/asm/ |
| D | ipic.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * IPIC external definitions and structure.
36 #define IPIC_SICNR 0x28 /* System Internal Interrupt Control Register */
37 #define IPIC_SEPNR 0x2C /* System External Interrupt Pending Register */
40 #define IPIC_SEMSR 0x38 /* System External Interrupt Mask Register */
41 #define IPIC_SECNR 0x3C /* System External Interrupt Control Register */
44 #define IPIC_SERCR 0x48 /* System Error Control Register */
47 #define IPIC_SEFCR 0x58 /* System External Interrupt Force Register */
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| /kernel/linux/linux-6.6/arch/powerpc/include/asm/ |
| D | ipic.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * IPIC external definitions and structure.
36 #define IPIC_SICNR 0x28 /* System Internal Interrupt Control Register */
37 #define IPIC_SEPNR 0x2C /* System External Interrupt Pending Register */
40 #define IPIC_SEMSR 0x38 /* System External Interrupt Mask Register */
41 #define IPIC_SECNR 0x3C /* System External Interrupt Control Register */
44 #define IPIC_SERCR 0x48 /* System Error Control Register */
47 #define IPIC_SEFCR 0x58 /* System External Interrupt Force Register */
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/usb/ |
| D | msm-hsusb.txt | 6 - compatible: Should contain "qcom,ehci-host"
7 - regs: offset and length of the register set in the memory map
8 - usb-phy: phandle for the PHY device
13 compatible = "qcom,ehci-host";
15 usb-phy = <&usb_otg>;
21 - compatible: Should contain:
22 "qcom,usb-otg-ci" for chipsets with ChipIdea 45nm PHY
23 "qcom,usb-otg-snps" for chipsets with Synopsys 28nm PHY
25 - regs: Offset and length of the register set in the memory map
26 - interrupts: interrupt-specifier for the OTG interrupt.
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/ |
| D | msm-hsusb.txt | 6 - compatible: Should contain "qcom,ehci-host"
7 - regs: offset and length of the register set in the memory map
8 - usb-phy: phandle for the PHY device
13 compatible = "qcom,ehci-host";
15 usb-phy = <&usb_otg>;
21 - compatible: Should contain:
22 "qcom,usb-otg-ci" for chipsets with ChipIdea 45nm PHY
23 "qcom,usb-otg-snps" for chipsets with Synopsys 28nm PHY
25 - regs: Offset and length of the register set in the memory map
26 - interrupts: interrupt-specifier for the OTG interrupt.
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/interrupt-controller/ |
| D | riscv,cpu-intc.txt | 1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
6 Some of these CSRs are used to control local interrupts connected to the core.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
11 attached to every HLIC: software interrupts, the timer interrupt, and external
13 timer interrupt comes from an architecturally mandated real-time timer that is
14 controlled via Supervisor Binary Interface (SBI) calls and CSR reads. External
16 via the platform-level interrupt controller (PLIC).
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | riscv,cpu-intc.txt | 1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
6 Some of these CSRs are used to control local interrupts connected to the core.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
11 attached to every HLIC: software interrupts, the timer interrupt, and external
13 timer interrupt comes from an architecturally mandated real-time timer that is
14 controlled via Supervisor Binary Interface (SBI) calls and CSR reads. External
16 via the platform-level interrupt controller (PLIC).
[all …]
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| /kernel/linux/linux-6.6/Documentation/networking/dsa/ |
| D | bcm_sf2.rst | 8 - xDSL gateways such as BCM63138
9 - streaming/multimedia Set Top Box such as BCM7445
10 - Cable Modem/residential gateways such as BCM7145/BCM3390
13 ports, offering a range of built-in and customizable interfaces:
15 - single integrated Gigabit PHY
16 - quad integrated Gigabit PHY
17 - quad external Gigabit PHY w/ MDIO multiplexer
18 - integrated MoCA PHY
19 - several external MII/RevMII/GMII/RGMII interfaces
21 The switch also supports specific congestion control features which allow MoCA
[all …]
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| /kernel/linux/linux-5.10/Documentation/networking/dsa/ |
| D | bcm_sf2.rst | 8 - xDSL gateways such as BCM63138
9 - streaming/multimedia Set Top Box such as BCM7445
10 - Cable Modem/residential gateways such as BCM7145/BCM3390
13 ports, offering a range of built-in and customizable interfaces:
15 - single integrated Gigabit PHY
16 - quad integrated Gigabit PHY
17 - quad external Gigabit PHY w/ MDIO multiplexer
18 - integrated MoCA PHY
19 - several external MII/RevMII/GMII/RGMII interfaces
21 The switch also supports specific congestion control features which allow MoCA
[all …]
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