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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/interconnect/
Dsamsung,exynos-bus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interconnect/samsung,exynos-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC Bus and Interconnect
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
14 The Samsung Exynos SoC has many buses for data transfer between DRAM and
15 sub-blocks in SoC. Most Exynos SoCs share the common architecture for buses.
16 Generally, each bus of Exynos SoC includes a source clock and a power line,
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/devfreq/
Dexynos-bus.txt1 * Generic Exynos Bus frequency device
3 The Samsung Exynos SoC has many buses for data transfer between DRAM
4 and sub-blocks in SoC. Most Exynos SoCs share the common architecture
5 for buses. Generally, each bus of Exynos SoC includes a source clock
7 of the bus in runtime. To monitor the usage of each bus in runtime,
9 is able to measure the current load of sub-blocks.
11 The Exynos SoC includes the various sub-blocks which have the each AXI bus.
12 The each AXI bus has the owned source clock but, has not the only owned
13 power line. The power line might be shared among one more sub-blocks.
14 So, we can divide into two type of device as the role of each sub-block.
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/exynos/
Dexynos5433-bus.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5433 SoC Memory interface and AMBA bus device tree source
11 compatible = "samsung,exynos-bus";
13 clock-names = "bus";
14 operating-points-v2 = <&bus_g2d_400_opp_table>;
19 compatible = "samsung,exynos-bus";
21 clock-names = "bus";
22 operating-points-v2 = <&bus_g2d_266_opp_table>;
27 compatible = "samsung,exynos-bus";
29 clock-names = "bus";
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/exynos/
Dexynos5433-bus.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5433 SoC Memory interface and AMBA bus device tree source
11 compatible = "samsung,exynos-bus";
13 clock-names = "bus";
14 operating-points-v2 = <&bus_g2d_400_opp_table>;
19 compatible = "samsung,exynos-bus";
21 clock-names = "bus";
22 operating-points-v2 = <&bus_g2d_266_opp_table>;
27 compatible = "samsung,exynos-bus";
29 clock-names = "bus";
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/samsung/
Dexynos5420.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 #include <dt-bindings/clock/exynos5420.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 bus_disp1: bus-disp1 {
38 compatible = "samsung,exynos-bus";
40 clock-names = "bus";
44 bus_disp1_fimd: bus-disp1-fimd {
45 compatible = "samsung,exynos-bus";
47 clock-names = "bus";
[all …]
Dexynos4210.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2010-2011 Linaro Ltd.
20 #include "exynos4-cpu-thermal.dtsi"
31 bus_acp: bus-acp {
32 compatible = "samsung,exynos-bus";
34 clock-names = "bus";
35 operating-points-v2 = <&bus_acp_opp_table>;
38 bus_acp_opp_table: opp-table {
39 compatible = "operating-points-v2";
[all …]
Dexynos4x12.dtsi1 // SPDX-License-Identifier: GPL-2.0
19 #include "exynos4-cpu-thermal.dtsi"
27 fimc-lite0 = &fimc_lite_0;
28 fimc-lite1 = &fimc_lite_1;
31 bus_acp: bus-acp {
32 compatible = "samsung,exynos-bus";
34 clock-names = "bus";
35 operating-points-v2 = <&bus_acp_opp_table>;
38 bus_acp_opp_table: opp-table {
39 compatible = "operating-points-v2";
[all …]
Dexynos3250.dtsi1 // SPDX-License-Identifier: GPL-2.0
17 #include "exynos4-cpu-thermal.dtsi"
18 #include <dt-bindings/clock/exynos3250.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 #include <dt-bindings/interrupt-controller/irq.h>
24 interrupt-parent = <&gic>;
25 #address-cells = <1>;
26 #size-cells = <1>;
46 bus_dmc: bus-dmc {
47 compatible = "samsung,exynos-bus";
[all …]
Dexynos4.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2010-2011 Linaro Ltd.
19 #include <dt-bindings/clock/exynos4.h>
20 #include <dt-bindings/clock/exynos-audss-clk.h>
21 #include <dt-bindings/interrupt-controller/arm-gic.h>
22 #include <dt-bindings/interrupt-controller/irq.h>
25 interrupt-parent = <&gic>;
26 #address-cells = <1>;
27 #size-cells = <1>;
[all …]
/kernel/linux/linux-6.6/drivers/devfreq/
Dexynos-bus.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Generic Exynos Bus frequency driver with DEVFREQ Framework
8 * This driver support Exynos Bus frequency feature by using
9 * DEVFREQ framework and is based on drivers/devfreq/exynos/exynos4_bus.c.
14 #include <linux/devfreq-event.h>
42 * Control the devfreq-event device to get the current state of bus
45 static int exynos_bus_##ops(struct exynos_bus *bus) \
49 for (i = 0; i < bus->edev_count; i++) { \
50 if (!bus->edev[i]) \
52 ret = devfreq_event_##ops(bus->edev[i]); \
[all …]
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
20 to a device by 1-to-1. The device registering devfreq takes the
39 Simple-Ondemand should be able to provide busy/total counter
79 tristate "ARM Exynos Generic Memory Bus DEVFREQ Driver"
86 This adds the common DEVFREQ driver for Exynos Memory bus. Exynos
87 Memory bus has one more group of memory bus (e.g, MIF and INT block).
88 Each memory bus group could contain many memoby bus block. It reads
89 PPMU counters of memory controllers by using DEVFREQ-event device
94 tristate "i.MX Generic Bus DEVFREQ Driver"
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dexynos5420.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 #include <dt-bindings/clock/exynos5420.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
42 * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
46 compatible = "operating-points-v2";
47 opp-shared;
49 opp-1800000000 {
50 opp-hz = /bits/ 64 <1800000000>;
51 opp-microvolt = <1250000 1250000 1500000>;
[all …]
Dexynos4210.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2010-2011 Linaro Ltd.
20 #include "exynos4-cpu-thermal.dtsi"
32 #address-cells = <1>;
33 #size-cells = <0>;
37 compatible = "arm,cortex-a9";
40 clock-names = "cpu";
41 clock-latency = <160000>;
43 operating-points = <
[all …]
Dexynos3250.dtsi1 // SPDX-License-Identifier: GPL-2.0
17 #include "exynos4-cpu-thermal.dtsi"
18 #include <dt-bindings/clock/exynos3250.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 #include <dt-bindings/interrupt-controller/irq.h>
24 interrupt-parent = <&gic>;
25 #address-cells = <1>;
26 #size-cells = <1>;
50 #address-cells = <1>;
51 #size-cells = <0>;
[all …]
Dexynos4412.dtsi1 // SPDX-License-Identifier: GPL-2.0
19 #include "exynos4-cpu-thermal.dtsi"
29 fimc-lite0 = &fimc_lite_0;
30 fimc-lite1 = &fimc_lite_1;
35 #address-cells = <1>;
36 #size-cells = <0>;
40 compatible = "arm,cortex-a9";
43 clock-names = "cpu";
44 operating-points-v2 = <&cpu0_opp_table>;
45 #cooling-cells = <2>; /* min followed by max */
[all …]
Dexynos4.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2010-2011 Linaro Ltd.
19 #include <dt-bindings/clock/exynos4.h>
20 #include <dt-bindings/clock/exynos-audss-clk.h>
21 #include <dt-bindings/interrupt-controller/arm-gic.h>
22 #include <dt-bindings/interrupt-controller/irq.h>
25 interrupt-parent = <&gic>;
26 #address-cells = <1>;
27 #size-cells = <1>;
[all …]
/kernel/linux/linux-5.10/drivers/devfreq/
Dexynos-bus.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Generic Exynos Bus frequency driver with DEVFREQ Framework
8 * This driver support Exynos Bus frequency feature by using
9 * DEVFREQ framework and is based on drivers/devfreq/exynos/exynos4_bus.c.
14 #include <linux/devfreq-event.h>
41 * Control the devfreq-event device to get the current state of bus
44 static int exynos_bus_##ops(struct exynos_bus *bus) \
48 for (i = 0; i < bus->edev_count; i++) { \
49 if (!bus->edev[i]) \
51 ret = devfreq_event_##ops(bus->edev[i]); \
[all …]
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
21 to a device by 1-to-1. The device registering devfreq takes the
40 Simple-Ondemand should be able to provide busy/total counter
80 tristate "ARM Exynos Generic Memory Bus DEVFREQ Driver"
87 This adds the common DEVFREQ driver for Exynos Memory bus. Exynos
88 Memory bus has one more group of memory bus (e.g, MIF and INT block).
89 Each memory bus group could contain many memoby bus block. It reads
90 PPMU counters of memory controllers by using DEVFREQ-event device
95 tristate "i.MX Generic Bus DEVFREQ Driver"
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/iommu/
Dsamsung,sysmmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit)
10 - Marek Szyprowski <m.szyprowski@samsung.com>
13 Samsung's Exynos architecture contains System MMUs that enables scattered
14 physical memory chunks visible as a contiguous region to DMA-capable peripheral
15 devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
20 another capabilities like L2 TLB or block-fetch buffers to minimize translation
24 peripheral device might have multiple System MMUs (usually one for each bus
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/iommu/
Dsamsung,sysmmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit)
10 - Marek Szyprowski <m.szyprowski@samsung.com>
13 Samsung's Exynos architecture contains System MMUs that enables scattered
14 physical memory chunks visible as a contiguous region to DMA-capable peripheral
15 devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
20 another capabilities like L2 TLB or block-fetch buffers to minimize translation
24 peripheral device might have multiple System MMUs (usually one for each bus
[all …]
/kernel/linux/linux-6.6/drivers/ufs/host/
DKconfig1 # SPDX-License-Identifier: GPL-2.0+
5 # Copyright (C) 2011-2013 Samsung India Software Operations
12 tristate "PCI bus based UFS Controller support"
31 tristate "Platform bus based UFS Controller support"
35 you have an UFS controller on Platform bus.
45 This selects the Cadence-specific additions to UFSHCD platform driver.
120 tristate "Exynos specific hooks to UFS controller platform driver"
123 This selects the Samsung Exynos SoC specific additions to UFSHCD
124 platform driver. UFS host on Samsung Exynos SoC includes HCI and
125 UNIPRO layer, and associates with UFS-PHY driver.
[all …]
/kernel/linux/linux-5.10/drivers/devfreq/event/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 bool "DEVFREQ-Event device Support"
5 The devfreq-event device provide the raw data and events which
6 indicate the current state of devfreq-event device. The provided
7 data from devfreq-event device is used to monitor the state of
11 The devfreq-event device can support the various type of events
18 tristate "Exynos NoC (Network On Chip) Probe DEVFREQ event Driver"
23 This add the devfreq-event driver for Exynos SoC. It provides NoC
24 (Network on Chip) Probe counters to measure the bandwidth of AXI bus.
27 tristate "Exynos PPMU (Platform Performance Monitoring Unit) DEVFREQ event Driver"
[all …]
/kernel/linux/linux-6.6/drivers/devfreq/event/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 bool "DEVFREQ-Event device Support"
5 The devfreq-event device provide the raw data and events which
6 indicate the current state of devfreq-event device. The provided
7 data from devfreq-event device is used to monitor the state of
11 The devfreq-event device can support the various type of events
18 tristate "Exynos NoC (Network On Chip) Probe DEVFREQ event Driver"
23 This add the devfreq-event driver for Exynos SoC. It provides NoC
24 (Network on Chip) Probe counters to measure the bandwidth of AXI bus.
27 tristate "Exynos PPMU (Platform Performance Monitoring Unit) DEVFREQ event Driver"
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/iio/adc/
Dsamsung,exynos-adc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/samsung,exynos-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos Analog to Digital Converter (ADC)
10 - Krzysztof Kozlowski <krzk@kernel.org>
15 - samsung,exynos-adc-v1 # Exynos5250
16 - samsung,exynos-adc-v2
17 - samsung,exynos3250-adc
18 - samsung,exynos4212-adc # Exynos4212 and Exynos4412
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/iio/adc/
Dsamsung,exynos-adc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/samsung,exynos-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos Analog to Digital Converter (ADC)
10 - Krzysztof Kozlowski <krzk@kernel.org>
15 - samsung,exynos-adc-v1 # Exynos5250
16 - samsung,exynos-adc-v2
17 - samsung,exynos3250-adc
18 - samsung,exynos4212-adc # Exynos4212 and Exynos4412
[all …]

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