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Searched +full:exynos4412 +full:- +full:isp +full:- +full:clock (Results 1 – 16 of 16) sorted by relevance

/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dexynos4-clock.txt1 * Samsung Exynos4 Clock Controller
3 The Exynos4 clock controller generates and supplies clock to various controllers
4 within the Exynos4 SoC. The clock binding described here is applicable to all
9 - compatible: should be one of the following.
10 - "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC.
11 - "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC.
13 - reg: physical base address of the controller and length of memory mapped
16 - #clock-cells: should be 1.
18 Each clock is assigned an identifier and client nodes can use this identifier
19 to specify the clock which they consume.
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dsamsung,exynos4412-isp-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos4412-isp-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos4412 SoC ISP clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Clock controller for Samsung Exynos4412 SoC FIMC-ISP (Camera ISP)
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Dsamsung,exynos-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
17 dt-bindings/clock/ headers.
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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dexynos4412.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4412 SoC device tree source
8 * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412
13 * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional
19 #include "exynos4-cpu-thermal.dtsi"
22 compatible = "samsung,exynos4412", "samsung,exynos4";
29 fimc-lite0 = &fimc_lite_0;
30 fimc-lite1 = &fimc_lite_1;
35 #address-cells = <1>;
36 #size-cells = <0>;
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Dexynos4412-galaxy-s3.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4412 based Galaxy S3 board device tree source
9 /dts-v1/;
10 #include "exynos4412-midas.dtsi"
20 flen-gpios = <&gpj1 1 GPIO_ACTIVE_HIGH>;
21 enset-gpios = <&gpj1 2 GPIO_ACTIVE_HIGH>;
23 pinctrl-names = "default", "host", "isp";
24 pinctrl-0 = <&camera_flash_host>;
25 pinctrl-1 = <&camera_flash_host>;
26 pinctrl-2 = <&camera_flash_isp>;
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/
Dexynos4-fimc-is.txt1 Exynos4x12 SoC series Imaging Subsystem (FIMC-IS)
3 The FIMC-IS is a subsystem for processing image signal from an image sensor.
4 The Exynos4x12 SoC series FIMC-IS V1.5 comprises of a dedicated ARM Cortex-A5
5 processor, ISP, DRC and FD IP blocks and peripheral devices such as UART, I2C
8 fimc-is node
9 ------------
12 - compatible : should be "samsung,exynos4212-fimc-is" for Exynos4212 and
13 Exynos4412 SoCs;
14 - reg : physical base address and length of the registers set;
15 - interrupts : must contain two FIMC-IS interrupts, in order: ISP0, ISP1;
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/kernel/linux/linux-6.6/arch/arm/boot/dts/samsung/
Dexynos4x12.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4412 SoC device tree source
19 #include "exynos4-cpu-thermal.dtsi"
27 fimc-lite0 = &fimc_lite_0;
28 fimc-lite1 = &fimc_lite_1;
31 bus_acp: bus-acp {
32 compatible = "samsung,exynos-bus";
33 clocks = <&clock CLK_DIV_ACP>;
34 clock-names = "bus";
35 operating-points-v2 = <&bus_acp_opp_table>;
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Dexynos4412-galaxy-s3.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4412 based Galaxy S3 board device tree source
9 /dts-v1/;
10 #include <dt-bindings/leds/common.h>
11 #include "exynos4412-midas.dtsi"
19 led-controller {
21 flen-gpios = <&gpj1 1 GPIO_ACTIVE_HIGH>;
22 enset-gpios = <&gpj1 2 GPIO_ACTIVE_HIGH>;
24 pinctrl-names = "default", "host", "isp";
25 pinctrl-0 = <&camera_flash_host>;
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/kernel/linux/linux-6.6/drivers/clk/samsung/
Dclk-exynos4412-isp.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Common Clock Framework support for Exynos4412 ISP module.
9 #include <dt-bindings/clock/exynos4.h>
12 #include <linux/clk-provider.h>
19 /* Exynos4x12 specific registers, which belong to ISP power domain */
25 /* NOTE: Must be equal to the last clock ID increased by one */
51 GATE(CLK_ISP_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0, 0, 0),
97 samsung_clk_save(ctx->reg_base, exynos4x12_save_isp, in exynos4x12_isp_clk_suspend()
106 samsung_clk_restore(ctx->reg_base, exynos4x12_save_isp, in exynos4x12_isp_clk_resume()
114 struct device *dev = &pdev->dev; in exynos4x12_isp_clk_probe()
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Samsung Clock specific Makefile
6 obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o clk-cpu.o
7 obj-$(CONFIG_EXYNOS_3250_COMMON_CLK) += clk-exynos3250.o
8 obj-$(CONFIG_EXYNOS_4_COMMON_CLK) += clk-exynos4.o
9 obj-$(CONFIG_EXYNOS_4_COMMON_CLK) += clk-exynos4412-isp.o
10 obj-$(CONFIG_EXYNOS_5250_COMMON_CLK) += clk-exynos5250.o
11 obj-$(CONFIG_EXYNOS_5250_COMMON_CLK) += clk-exynos5-subcmu.o
12 obj-$(CONFIG_EXYNOS_5260_COMMON_CLK) += clk-exynos5260.o
13 obj-$(CONFIG_EXYNOS_5410_COMMON_CLK) += clk-exynos5410.o
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/kernel/linux/linux-5.10/drivers/clk/samsung/
Dclk-exynos4412-isp.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Common Clock Framework support for Exynos4412 ISP module.
9 #include <dt-bindings/clock/exynos4.h>
12 #include <linux/clk-provider.h>
19 /* Exynos4x12 specific registers, which belong to ISP power domain */
48 GATE(CLK_ISP_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0, 0, 0),
94 samsung_clk_save(ctx->reg_base, exynos4x12_save_isp, in exynos4x12_isp_clk_suspend()
103 samsung_clk_restore(ctx->reg_base, exynos4x12_save_isp, in exynos4x12_isp_clk_resume()
111 struct device *dev = &pdev->dev; in exynos4x12_isp_clk_probe()
112 struct device_node *np = dev->of_node; in exynos4x12_isp_clk_probe()
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Samsung Clock specific Makefile
6 obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o clk-cpu.o
7 obj-$(CONFIG_SOC_EXYNOS3250) += clk-exynos3250.o
8 obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
9 obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4412-isp.o
10 obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
11 obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5-subcmu.o
12 obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o
13 obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
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/kernel/linux/linux-5.10/include/dt-bindings/clock/
Dexynos4.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Device Tree binding constants for Exynos4 clock controller.
54 #define CLK_SCLK_MDNIE0 141 /* Exynos4412 only */
82 #define CLK_SCLK_MIPIHSI 169 /* Exynos4412 only */
123 #define CLK_MDNIE0 285 /* Exynos4412 only */
213 /* gate clocks - ppmu */
240 /* must be greater than maximal clock id */
243 /* Exynos4x12 ISP clocks */
/kernel/linux/linux-6.6/include/dt-bindings/clock/
Dexynos4.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Device Tree binding constants for Exynos4 clock controller.
54 #define CLK_SCLK_MDNIE0 141 /* Exynos4412 only */
82 #define CLK_SCLK_MIPIHSI 169 /* Exynos4412 only */
123 #define CLK_MDNIE0 285 /* Exynos4412 only */
214 /* gate clocks - ppmu */
242 /* Exynos4x12 ISP clocks */
/kernel/linux/linux-5.10/drivers/media/platform/exynos4-is/
Dfimc-core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2010-2012 Samsung Electronics Co., Ltd.
25 #include <media/v4l2-ioctl.h>
26 #include <media/videobuf2-v4l2.h>
27 #include <media/videobuf2-dma-contig.h>
29 #include "fimc-core.h"
30 #include "fimc-reg.h"
31 #include "media-dev.h"
198 if (!ctx->scaler.enabled) in fimc_check_scaler_ratio()
199 return (sw == dw && sh == dh) ? 0 : -EINVAL; in fimc_check_scaler_ratio()
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/kernel/linux/linux-6.6/drivers/media/platform/samsung/exynos4-is/
Dfimc-core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2010-2012 Samsung Electronics Co., Ltd.
24 #include <media/v4l2-ioctl.h>
25 #include <media/videobuf2-v4l2.h>
26 #include <media/videobuf2-dma-contig.h>
28 #include "fimc-core.h"
29 #include "fimc-reg.h"
30 #include "media-dev.h"
197 if (!ctx->scaler.enabled) in fimc_check_scaler_ratio()
198 return (sw == dw && sh == dh) ? 0 : -EINVAL; in fimc_check_scaler_ratio()
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