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Searched +full:exynos5433 +full:- +full:cmu +full:- +full:isp (Results 1 – 9 of 9) sorted by relevance

/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dsamsung,exynos5433-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos5433-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos5433 SoC clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dexynos5433-clock.txt1 * Samsung Exynos5433 CMU (Clock Management Units)
3 The Exynos5433 clock controller generates and supplies clock to various
4 controllers within the Exynos5433 SoC.
8 - compatible: should be one of the following.
9 - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP
12 - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF
14 - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF
16 - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC
18 - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS
20 - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/exynos/
Dexynos5433.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5433 SoC device tree source
7 * Samsung's Exynos5433 SoC device nodes are listed in this file.
8 * Exynos5433 based board files can include this file and provide
12 * Exynos5433 SoC. As device tree coverage for Exynos5433 increases,
16 #include <dt-bindings/clock/exynos5433.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 compatible = "samsung,exynos5433";
21 #address-cells = <2>;
22 #size-cells = <2>;
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/kernel/linux/linux-6.6/arch/arm64/boot/dts/exynos/
Dexynos5433.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5433 SoC device tree source
7 * Samsung's Exynos5433 SoC device nodes are listed in this file.
8 * Exynos5433 based board files can include this file and provide
12 * Exynos5433 SoC. As device tree coverage for Exynos5433 increases,
16 #include <dt-bindings/clock/exynos5433.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 compatible = "samsung,exynos5433";
21 #address-cells = <2>;
22 #size-cells = <2>;
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/samsung/
Dsamsung-soc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/samsung/samsung-soc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
15 samsung,SoC-IP
18 samsung,exynos5433-cmu-isp
23 pattern: "^samsung,.*(s3c|s5pv|exynos)[0-9a-z]+.*$"
25 - compatible
30 - description: Preferred naming style for compatibles of SoC components
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/devfreq/
Dexynos-bus.txt4 and sub-blocks in SoC. Most Exynos SoCs share the common architecture
9 is able to measure the current load of sub-blocks.
11 The Exynos SoC includes the various sub-blocks which have the each AXI bus.
13 power line. The power line might be shared among one more sub-blocks.
14 So, we can divide into two type of device as the role of each sub-block.
16 - parent bus device
17 - passive bus device
26 VDD_xxx |--- A block (parent)
27 |--- B block (passive)
28 |--- C block (passive)
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/interconnect/
Dsamsung,exynos-bus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interconnect/samsung,exynos-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
15 sub-blocks in SoC. Most Exynos SoCs share the common architecture for buses.
20 sub-blocks.
22 The Exynos SoC includes the various sub-blocks which have the each AXI bus.
24 line. The power line might be shared among one more sub-blocks. So, we can
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/kernel/linux/linux-5.10/drivers/clk/samsung/
Dclk-exynos5433.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Common Clock Framework support for Exynos5433 SoC.
10 #include <linux/clk-provider.h>
18 #include <dt-bindings/clock/exynos5433.h>
21 #include "clk-cpu.h"
22 #include "clk-pll.h"
183 /* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */
185 /* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */
769 PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690),
771 PLL_36XX_RATE(24 * MHZ, 368639991U, 246, 4, 2, -15729),
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/kernel/linux/linux-6.6/drivers/clk/samsung/
Dclk-exynos5433.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Common Clock Framework support for Exynos5433 SoC.
10 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/exynos5433.h>
20 #include "clk-cpu.h"
21 #include "clk-exynos-arm64.h"
22 #include "clk-pll.h"
206 /* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */
208 /* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */
792 PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690),
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