Home
last modified time | relevance | path

Searched +full:exynos5433 +full:- +full:uart (Results 1 – 18 of 18) sorted by relevance

/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dexynos5433-clock.txt1 * Samsung Exynos5433 CMU (Clock Management Units)
3 The Exynos5433 clock controller generates and supplies clock to various
4 controllers within the Exynos5433 SoC.
8 - compatible: should be one of the following.
9 - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP
12 - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF
14 - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF
16 - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC
17 which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs.
18 - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mfd/
Dsamsung,exynos5433-lpass.txt5 - compatible : "samsung,exynos5433-lpass"
6 - reg : should contain the LPASS top SFR region location
8 - clock-names : should contain following required clocks: "sfr0_ctrl"
9 - clocks : should contain clock specifiers of all clocks, which
10 input names have been specified in clock-names
12 - #address-cells : should be 1
13 - #size-cells : should be 1
14 - ranges : must be present
17 an optional sub-node. For "samsung,exynos5433-lpass" compatible this includes:
18 UART, SLIMBUS, PCM, I2S, DMAC, Timers 0...4, VIC, WDT 0...1 devices.
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mfd/
Dsamsung,exynos5433-lpass.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/samsung,exynos5433-lpass.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
15 const: samsung,exynos5433-lpass
17 '#address-cells':
23 clock-names:
25 - const: sfr0_ctrl
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/serial/
Dsamsung_uart.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S3C, S5P, Exynos, and S5L (Apple SoC) SoC UART Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
14 Each Samsung UART should have an alias correctly numbered in the "aliases"
15 node, according to serialN format, where N is the port number (non-negative
21 - items:
22 - const: samsung,exynosautov9-uart
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/exynos/
Dexynos5433.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5433 SoC device tree source
7 * Samsung's Exynos5433 SoC device nodes are listed in this file.
8 * Exynos5433 based board files can include this file and provide
12 * Exynos5433 SoC. As device tree coverage for Exynos5433 increases,
16 #include <dt-bindings/clock/exynos5433.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 compatible = "samsung,exynos5433";
21 #address-cells = <2>;
22 #size-cells = <2>;
[all …]
Dexynos7.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/exynos7-clk.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
31 arm-pmu {
32 compatible = "arm,cortex-a57-pmu";
37 interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>,
43 compatible = "fixed-clock";
[all …]
Dexynos5433-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device
12 #include <dt-bindings/pinctrl/samsung.h>
17 samsung,pin-function = <EXYNOS_PIN_FUNC_ ##_func>; \
18 samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \
19 samsung,pin-drv = <EXYNOS5433_PIN_DRV_ ##_drv>; \
24 gpio-controller;
25 #gpio-cells = <2>;
27 interrupt-controller;
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/exynos/
Dexynos5433.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5433 SoC device tree source
7 * Samsung's Exynos5433 SoC device nodes are listed in this file.
8 * Exynos5433 based board files can include this file and provide
12 * Exynos5433 SoC. As device tree coverage for Exynos5433 increases,
16 #include <dt-bindings/clock/exynos5433.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 compatible = "samsung,exynos5433";
21 #address-cells = <2>;
22 #size-cells = <2>;
[all …]
Dexynos7885.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/exynos7885.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #address-cells = <2>;
15 #size-cells = <1>;
17 interrupt-parent = <&gic>;
26 arm-a53-pmu {
27 compatible = "arm,cortex-a53-pmu";
34 interrupt-affinity = <&cpu0>,
42 arm-a73-pmu {
[all …]
Dexynos5433-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 pin- ## _pin { \
17 samsung,pin-function = <EXYNOS_PIN_FUNC_ ##_func>; \
18 samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \
19 samsung,pin-drv = <EXYNOS5433_PIN_DRV_ ##_drv>; \
32 gpa0: gpa0-gpio-bank {
33 gpio-controller;
[all …]
Dexynos7.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/exynos7-clk.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
31 arm-pmu {
32 compatible = "arm,cortex-a57-pmu";
37 interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>,
43 compatible = "fixed-clock";
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dsamsung,exynos5433-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos5433-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos5433 SoC clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/
Dsamsung-pinctrl.txt6 on-chip controllers onto these pads.
9 - compatible: should be one of the following.
10 - "samsung,s3c2412-pinctrl": for S3C2412-compatible pin-controller,
11 - "samsung,s3c2416-pinctrl": for S3C2416-compatible pin-controller,
12 - "samsung,s3c2440-pinctrl": for S3C2440-compatible pin-controller,
13 - "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller,
14 - "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller,
15 - "samsung,s5pv210-pinctrl": for S5PV210-compatible pin-controller,
16 - "samsung,exynos3250-pinctrl": for Exynos3250 compatible pin-controller.
17 - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
[all …]
/kernel/linux/linux-6.6/drivers/mfd/
Dexynos-lpass.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 - 2016 Samsung Electronics Co., Ltd.
11 * devices for IP blocks like DMAC, I2S, UART.
23 #include <linux/soc/samsung/exynos-regs-pmu.h>
61 regmap_read(lpass->top, SFR_LPASS_CORE_SW_RESET, &val); in exynos_lpass_core_sw_reset()
64 regmap_write(lpass->top, SFR_LPASS_CORE_SW_RESET, val); in exynos_lpass_core_sw_reset()
69 regmap_write(lpass->top, SFR_LPASS_CORE_SW_RESET, val); in exynos_lpass_core_sw_reset()
74 clk_prepare_enable(lpass->sfr0_clk); in exynos_lpass_enable()
77 regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, in exynos_lpass_enable()
80 regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK, in exynos_lpass_enable()
[all …]
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
45 tristate "Active-semi ACT8945A"
50 Support for the ACT8945A PMIC from Active-semi. This device
51 features three step-down DC/DC converters and four low-dropout
67 sun4i-gpadc-iio and the hwmon driver iio_hwmon.
70 called sun4i-gpadc.
101 tablets etc. It has 4 DC/DC step-down regulators, 3 DC/DC step-down
132 over at91-usart-serial driver and usart-spi-driver. Only one function
148 tristate "Atmel HLCDC (High-end LCD Controller)"
185 tristate "X-Powers AC100"
[all …]
/kernel/linux/linux-5.10/drivers/mfd/
Dexynos-lpass.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 - 2016 Samsung Electronics Co., Ltd.
11 * devices for IP blocks like DMAC, I2S, UART.
24 #include <linux/soc/samsung/exynos-regs-pmu.h>
62 regmap_read(lpass->top, SFR_LPASS_CORE_SW_RESET, &val); in exynos_lpass_core_sw_reset()
65 regmap_write(lpass->top, SFR_LPASS_CORE_SW_RESET, val); in exynos_lpass_core_sw_reset()
70 regmap_write(lpass->top, SFR_LPASS_CORE_SW_RESET, val); in exynos_lpass_core_sw_reset()
75 clk_prepare_enable(lpass->sfr0_clk); in exynos_lpass_enable()
78 regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, in exynos_lpass_enable()
81 regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK, in exynos_lpass_enable()
[all …]
/kernel/linux/linux-5.10/drivers/tty/serial/
Dsamsung_tty.c1 // SPDX-License-Identifier: GPL-2.0
5 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
12 * UERSTAT register in the UART blocks, and keeps marking some of the
21 * BJD, 04-Nov-2004
25 #include <linux/dma-mapping.h>
45 /* UART name and device definitions */
74 /* uart port features */
153 #define portaddr(port, reg) ((port)->membase + (reg))
155 ((unsigned long *)(unsigned long)((port)->membase + (reg)))
159 switch (port->iotype) { in rd_reg()
[all …]
/kernel/linux/linux-6.6/drivers/tty/serial/
Dsamsung_tty.c1 // SPDX-License-Identifier: GPL-2.0
5 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
12 * UERSTAT register in the UART blocks, and keeps marking some of the
21 * BJD, 04-Nov-2004
25 #include <linux/dma-mapping.h>
46 /* UART name and device definitions */
89 /* uart port features */
166 #define portaddr(port, reg) ((port)->membase + (reg))
168 ((unsigned long *)(unsigned long)((port)->membase + (reg)))
172 switch (port->iotype) { in rd_reg()
[all …]