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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/tegra/
Dnvidia,nvec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
26 - description: divider clock
27 - description: fast clock
29 clock-names:
32 - const: div-clk
33 - const: fast-clk
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/i2c/
Dnvidia,tegra20-i2c.txt4 - compatible : For Tegra20, must be one of "nvidia,tegra20-i2c-dvc" or
5 "nvidia,tegra20-i2c". For Tegra30, must be "nvidia,tegra30-i2c".
6 For Tegra114, must be "nvidia,tegra114-i2c". Otherwise, must be
7 "nvidia,<chip>-i2c", plus at least one of the above, where <chip> is
10 nvidia,tegra20-i2c-dvc: Tegra20 has specific I2C controller called as DVC I2C
14 "nvidia,tegra20-i2c-dvc".
15 nvidia,tegra20-i2c: Tegra20 has 4 generic I2C controller. This can support
16 master and slave mode of I2C communication. The i2c-tegra driver only
18 only compatible with "nvidia,tegra20-i2c".
19 nvidia,tegra30-i2c: Tegra30 has 5 generic I2C controller. This controller is
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dste-u300.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree for the ST-Ericsson U300 Machine and SoC
6 /dts-v1/;
9 model = "ST-Ericsson U300";
11 #address-cells = <1>;
12 #size-cells = <1>;
30 vana15-supply = <&ab3100_ldo_d_reg>;
35 compatible = "stericsson,u300-syscon", "syscon";
38 #clock-cells = <0>;
39 compatible = "fixed-clock";
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Dqcom-msm8974-sony-xperia-castor.dts1 #include "qcom-msm8974pro.dtsi"
2 #include "qcom-pm8841.dtsi"
3 #include "qcom-pm8941.dtsi"
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
10 compatible = "sony,xperia-castor", "qcom,msm8974";
17 stdout-path = "serial0:115200n8";
20 gpio-keys {
21 compatible = "gpio-keys";
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/i2c/
Dnvidia,tegra20-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/nvidia,tegra20-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 - Thierry Reding <thierry.reding@gmail.com>
9 - Jon Hunter <jonathanh@nvidia.com>
16 - description: Tegra20 has 4 generic I2C controller. This can support
17 master and slave mode of I2C communication. The i2c-tegra driver
19 controller is only compatible with "nvidia,tegra20-i2c".
20 const: nvidia,tegra20-i2c
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/kernel/linux/linux-6.6/arch/arm64/boot/dts/exynos/
Dexynos7885-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Exynos7885 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos7885 SoC pin-mux and pin-config options are listed as
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include "exynos-pinctrl.h"
16 etc0: etc0-gpio-bank {
17 gpio-controller;
18 #gpio-cells = <2>;
20 interrupt-controller;
21 #interrupt-cells = <2>;
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/kernel/linux/linux-5.10/drivers/net/mdio/
Dmdio-hisi-femac.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Hisilicon Fast Ethernet MDIO Bus Driver
8 #include <linux/clk.h>
24 struct clk *clk; member
32 return readl_poll_timeout(data->membase + MDIO_RWCTRL, in hisi_femac_mdio_wait_ready()
38 struct hisi_femac_mdio_data *data = bus->priv; in hisi_femac_mdio_read()
46 data->membase + MDIO_RWCTRL); in hisi_femac_mdio_read()
52 return readl(data->membase + MDIO_RO_DATA) & 0xFFFF; in hisi_femac_mdio_read()
58 struct hisi_femac_mdio_data *data = bus->priv; in hisi_femac_mdio_write()
67 data->membase + MDIO_RWCTRL); in hisi_femac_mdio_write()
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/kernel/linux/linux-6.6/drivers/net/mdio/
Dmdio-hisi-femac.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Hisilicon Fast Ethernet MDIO Bus Driver
8 #include <linux/clk.h>
24 struct clk *clk; member
32 return readl_poll_timeout(data->membase + MDIO_RWCTRL, in hisi_femac_mdio_wait_ready()
38 struct hisi_femac_mdio_data *data = bus->priv; in hisi_femac_mdio_read()
46 data->membase + MDIO_RWCTRL); in hisi_femac_mdio_read()
52 return readl(data->membase + MDIO_RO_DATA) & 0xFFFF; in hisi_femac_mdio_read()
58 struct hisi_femac_mdio_data *data = bus->priv; in hisi_femac_mdio_write()
67 data->membase + MDIO_RWCTRL); in hisi_femac_mdio_write()
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/kernel/linux/linux-5.10/arch/arm/mach-u300/
Dcore.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * arch/arm/mach-u300/core.c
6 * Copyright (C) 2007-2012 ST-Ericsson SA
12 #include <linux/pinctrl/pinconf-generic.h>
13 #include <linux/platform_data/clk-u300.h>
18 #include <linux/clk.h>
38 /* FAST Peripherals */
68 * FAST peripherals
71 /* FAST bridge control */
85 /* Fast UART1 on U335 only */
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/kernel/linux/linux-6.6/drivers/bus/
Dqcom-ebi2.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/clk.h>
41 * Bits 31-28: RECOVERY recovery cycles (0 = 1, 1 = 2 etc) this is the time the
42 * memory continues to drive the data bus after OE is de-asserted.
45 * Bits 27-24: WR_HOLD write hold cycles, these are extra cycles inserted after
49 * Bits 23-16: WR_DELTA initial latency for write cycles inserted for the first
51 * Bits 15-8: RD_DELTA initial latency for read cycles inserted for the first
53 * Bits 7-4: WR_WAIT number of wait cycles for every write access, 0=1 cycle
55 * Bits 3-0: RD_WAIT number of wait cycles for every read access, 0=1 cycle
73 * FAST CSn CFG
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/kernel/linux/linux-5.10/drivers/bus/
Dqcom-ebi2.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/clk.h>
41 * Bits 31-28: RECOVERY recovery cycles (0 = 1, 1 = 2 etc) this is the time the
42 * memory continues to drive the data bus after OE is de-asserted.
45 * Bits 27-24: WR_HOLD write hold cycles, these are extra cycles inserted after
49 * Bits 23-16: WR_DELTA initial latency for write cycles inserted for the first
51 * Bits 15-8: RD_DELTA initial latency for read cycles inserted for the first
53 * Bits 7-4: WR_WAIT number of wait cycles for every write access, 0=1 cycle
55 * Bits 3-0: RD_WAIT number of wait cycles for every read access, 0=1 cycle
73 * FAST CSn CFG
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dste-u300-syscon-clock.txt1 Clock bindings for ST-Ericsson U300 System Controller Clocks
6 - compatible: must be "stericsson,u300-syscon-clk"
7 - #clock-cells: must be <0>
8 - clock-type: specifies the type of clock:
10 1 = fast clock
12 - clock-id: specifies the clock in the type range
15 - clocks: parent clock(s)
20 -------------------
28 1 0 Fast peripheral bridge clock
46 #clock-cells = <0>;
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/kernel/linux/linux-5.10/drivers/i2c/busses/
Di2c-stm32f4.c1 // SPDX-License-Identifier: GPL-2.0
13 * This driver is based on i2c-st.c
17 #include <linux/clk.h>
31 #include "i2c-stm32.h"
97 * struct stm32f4_i2c_msg - client specific data
98 * @addr: 8-bit slave addr, including r/w bit
113 * struct stm32f4_i2c_dev - private data of the controller
118 * @clk: hw i2c clock
119 * @speed: I2C clock frequency of the controller. Standard or Fast are supported
128 struct clk *clk; member
[all …]
Di2c-designware-core.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
178 struct clk;
183 * struct dw_i2c_dev - private i2c-designware data
190 * @clk: input reference clock
212 * @rx_outstanding: current master-rx elements in tx fifo
217 * @fs_hcnt: fast speed HCNT value
218 * @fs_lcnt: fast speed LCNT value
219 * @fp_hcnt: fast plus HCNT value
220 * @fp_lcnt: fast plus LCNT value
229 * @mode: operation mode - DW_IC_MASTER or DW_IC_SLAVE
[all …]
Di2c-uniphier-f.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk.h>
82 struct clk *clk; member
99 * TX-FIFO stores slave address in it for the first access. in uniphier_fi2c_fill_txfifo()
103 fifo_space--; in uniphier_fi2c_fill_txfifo()
105 while (priv->len) { in uniphier_fi2c_fill_txfifo()
106 if (fifo_space-- <= 0) in uniphier_fi2c_fill_txfifo()
109 writel(*priv->buf++, priv->membase + UNIPHIER_FI2C_DTTX); in uniphier_fi2c_fill_txfifo()
110 priv->len--; in uniphier_fi2c_fill_txfifo()
116 int fifo_left = priv->flags & UNIPHIER_FI2C_BYTE_WISE ? in uniphier_fi2c_drain_rxfifo()
[all …]
Di2c-nomadik.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2009 ST-Ericsson SA
19 #include <linux/clk.h>
25 #define DRIVER_NAME "nmk-i2c"
61 #define I2C_MCR_A7 (0x7f << 1) /* 7-bit address */
62 #define I2C_MCR_EA10 (0x7 << 8) /* 10-bit Extended address */
111 * struct i2c_vendor_data - per-vendor variations
135 * struct i2c_nmk_client - client specific data
136 * @slave_adr: 7-bit slave address
151 * struct nmk_i2c_dev - private data structure of the controller.
[all …]
/kernel/linux/linux-6.6/drivers/i2c/busses/
Di2c-stm32f4.c1 // SPDX-License-Identifier: GPL-2.0
13 * This driver is based on i2c-st.c
17 #include <linux/clk.h>
31 #include "i2c-stm32.h"
97 * struct stm32f4_i2c_msg - client specific data
98 * @addr: 8-bit slave addr, including r/w bit
113 * struct stm32f4_i2c_dev - private data of the controller
118 * @clk: hw i2c clock
119 * @speed: I2C clock frequency of the controller. Standard or Fast are supported
128 struct clk *clk; member
[all …]
Di2c-designware-core.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
188 struct clk;
193 * struct dw_i2c_dev - private i2c-designware data
200 * @clk: input reference clock
225 * @rx_outstanding: current master-rx elements in tx fifo
230 * @fs_hcnt: fast speed HCNT value
231 * @fs_lcnt: fast speed LCNT value
232 * @fp_hcnt: fast plus HCNT value
233 * @fp_lcnt: fast plus LCNT value
239 * -1 if there is no semaphore.
[all …]
Di2c-uniphier-f.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk.h>
82 struct clk *clk; member
99 * TX-FIFO stores slave address in it for the first access. in uniphier_fi2c_fill_txfifo()
103 fifo_space--; in uniphier_fi2c_fill_txfifo()
105 while (priv->len) { in uniphier_fi2c_fill_txfifo()
106 if (fifo_space-- <= 0) in uniphier_fi2c_fill_txfifo()
109 writel(*priv->buf++, priv->membase + UNIPHIER_FI2C_DTTX); in uniphier_fi2c_fill_txfifo()
110 priv->len--; in uniphier_fi2c_fill_txfifo()
116 int fifo_left = priv->flags & UNIPHIER_FI2C_BYTE_WISE ? in uniphier_fi2c_drain_rxfifo()
[all …]
Di2c-nomadik.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2009 ST-Ericsson SA
19 #include <linux/clk.h>
25 #define DRIVER_NAME "nmk-i2c"
61 #define I2C_MCR_A7 (0x7f << 1) /* 7-bit address */
62 #define I2C_MCR_EA10 (0x7 << 8) /* 10-bit Extended address */
111 * struct i2c_vendor_data - per-vendor variations
135 * struct i2c_nmk_client - client specific data
136 * @slave_adr: 7-bit slave address
151 * struct nmk_i2c_dev - private data structure of the controller.
[all …]
Di2c-rk3x.c1 // SPDX-License-Identifier: GPL-2.0-only
21 #include <linux/clk.h>
83 * struct i2c_spec_values - I2C specification values for various modes
87 * @min_setup_start_ns: min set-up time for a repeated START conditio
89 * @min_data_setup_ns: min data set-up time
90 * @min_setup_stop_ns: min set-up time for STOP condition
139 * struct rk3x_i2c_calced_timings - calculated V1 timings
162 * struct rk3x_i2c_soc_data - SOC-specific data
173 * struct rk3x_i2c - private data of the controller
178 * @clk: function clk for rk3399 or function & Bus clks for others
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,nvec.txt4 - compatible : should be "nvidia,nvec".
5 - reg : the iomem of the i2c slave controller
6 - interrupts : the interrupt line of the i2c slave controller
7 - clock-frequency : the frequency of the i2c bus
8 - gpios : the gpio used for ec request
9 - slave-addr: the i2c address of the slave controller
10 - clocks : Must contain an entry for each entry in clock-names.
11 See ../clocks/clock-bindings.txt for details.
12 - clock-names : Must include the following entries:
14 - div-clk
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/kernel/linux/linux-5.10/drivers/scsi/ufs/
Dufs-qcom.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
8 #include <linux/reset-controller.h>
26 /* vendor specific pre-defined parameters */
28 #define FAST 2 macro
41 #define UFS_QCOM_LIMIT_DESIRED_MODE FAST
171 * Make sure de-assertion of ufs phy reset is written to in ufs_qcom_deassert_reset()
210 struct clk *rx_l0_sync_clk;
211 struct clk *tx_l0_sync_clk;
212 struct clk *rx_l1_sync_clk;
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/kernel/linux/linux-5.10/drivers/spi/
Dspi-dw-bt1.c1 // SPDX-License-Identifier: GPL-2.0-only
9 // Baikal-T1 DW APB SPI and System Boot SPI driver
12 #include <linux/clk.h>
24 #include <linux/spi/spi-mem.h>
27 #include "spi-dw.h"
34 struct clk *clk; member
52 struct dw_spi_bt1 *dwsbt1 = to_dw_spi_bt1(desc->mem->spi->controller); in dw_spi_bt1_dirmap_create()
54 if (!dwsbt1->map || in dw_spi_bt1_dirmap_create()
55 !dwsbt1->dws.mem_ops.supports_op(desc->mem, &desc->info.op_tmpl)) in dw_spi_bt1_dirmap_create()
56 return -EOPNOTSUPP; in dw_spi_bt1_dirmap_create()
[all …]
/kernel/linux/linux-6.6/drivers/spi/
Dspi-dw-bt1.c1 // SPDX-License-Identifier: GPL-2.0-only
9 // Baikal-T1 DW APB SPI and System Boot SPI driver
12 #include <linux/clk.h>
24 #include <linux/spi/spi-mem.h>
27 #include "spi-dw.h"
34 struct clk *clk; member
52 struct dw_spi_bt1 *dwsbt1 = to_dw_spi_bt1(desc->mem->spi->controller); in dw_spi_bt1_dirmap_create()
54 if (!dwsbt1->map || in dw_spi_bt1_dirmap_create()
55 !dwsbt1->dws.mem_ops.supports_op(desc->mem, &desc->info.op_tmpl)) in dw_spi_bt1_dirmap_create()
56 return -EOPNOTSUPP; in dw_spi_bt1_dirmap_create()
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