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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Dti,dp83822.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Andrew Davis <afd@ti.com>
14 The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It
16 data over standard, twisted-pair cables or to connect to an external,
17 fiber-optic transceiver. Additionally, the DP83822 provides flexibility to
24 - $ref: ethernet-phy.yaml#
30 ti,link-loss-low:
33 DP83822 PHY in Fiber mode only.
[all …]
Dmicrel.txt7 - micrel,led-mode : LED mode value to set for PHYs with configurable LEDs.
9 Configure the LED mode with single value. The list of PHYs and the
21 See the respective PHY datasheet for the mode values.
23 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
24 bit selects 25 MHz mode
27 than 50 MHz clock mode.
30 non-standard, inverted function of this configuration bit.
31 Specifically, a clock reference ("rmii-ref" below) is always needed to
32 actually select a mode.
34 - clocks, clock-names: contains clocks according to the common clock bindings.
[all …]
Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <afd@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
22 SGMII The DP83869HM supports Media Conversion in Managed mode. In this mode,
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dti,dp83822.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Dan Murphy <dmurphy@ti.com>
14 The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It
16 data over standard, twisted-pair cables or to connect to an external,
17 fiber-optic transceiver. Additionally, the DP83822 provides flexibility to
24 - $ref: "ethernet-phy.yaml#"
30 ti,link-loss-low:
33 DP83822 PHY in Fiber mode only.
[all …]
Dmicrel.txt7 - micrel,led-mode : LED mode value to set for PHYs with configurable LEDs.
9 Configure the LED mode with single value. The list of PHYs and the
20 See the respective PHY datasheet for the mode values.
22 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
23 bit selects 25 MHz mode
26 than 50 MHz clock mode.
29 non-standard, inverted function of this configuration bit.
30 Specifically, a clock reference ("rmii-ref" below) is always needed to
31 actually select a mode.
33 - clocks, clock-names: contains clocks according to the common clock bindings.
[all …]
Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - $ref: "ethernet-phy.yaml#"
14 - Dan Murphy <dmurphy@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
22 SGMII The DP83869HM supports Media Conversion in Managed mode. In this mode,
[all …]
/kernel/linux/linux-6.6/drivers/net/phy/
Dmotorcomm.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Author: Frank <Frank.Sae@motor-comm.com>
21 * UTP Register space | FIBER Register space
22 * ------------------------------------------------------------
23 * | UTP MII | FIBER MII |
25 * | UTP Extended | FIBER Extended |
26 * ------------------------------------------------------------
28 * ------------------------------------------------------------
104 /* FIBER Auto-Negotiation link partner ability */
125 /* TX Gig-E Delay is bits 7:4, default 0x5
[all …]
Dmarvell.c1 // SPDX-License-Identifier: GPL-2.0+
188 /* RGMII to 1000BASE-X */
190 /* RGMII to 100BASE-FX */
347 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in marvell_config_intr()
411 err = marvell_set_polarity(phydev, phydev->mdix_ctrl); in marvell_config_aneg()
426 if (phydev->autoneg != AUTONEG_ENABLE || changed) { in marvell_config_aneg()
476 * marvell,reg-init property stored in the of_node for the phydev.
478 * marvell,reg-init = <reg-page reg mask value>,...;
480 * There may be one or more sets of <reg-page reg mask value>:
482 * reg-page: which register bank to use.
[all …]
Dlxt.c1 // SPDX-License-Identifier: GPL-2.0+
44 /* ------------------------------------------------------------------------- */
83 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in lxt970_config_intr()
147 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in lxt971_config_intr()
206 } while (status >= 0 && retry-- && status == control); in lxt973a2_update_link()
212 phydev->link = 0; in lxt973a2_update_link()
214 phydev->link = 1; in lxt973a2_update_link()
230 if (AUTONEG_ENABLE == phydev->autoneg) { in lxt973a2_read_status()
247 } while (lpa == adv && retry--); in lxt973a2_read_status()
249 mii_lpa_to_linkmode_lpa_t(phydev->lp_advertising, lpa); in lxt973a2_read_status()
[all …]
Ddp83822.c1 // SPDX-License-Identifier: GPL-2.0
102 /* SOR1 mode */
126 struct net_device *ndev = phydev->attached_dev; in dp83822_set_wol()
130 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) { in dp83822_set_wol()
131 mac = (const u8 *)ndev->dev_addr; in dp83822_set_wol()
134 return -EINVAL; in dp83822_set_wol()
148 if (wol->wolopts & WAKE_MAGIC) in dp83822_set_wol()
153 if (wol->wolopts & WAKE_MAGICSECURE) { in dp83822_set_wol()
156 (wol->sopass[1] << 8) | wol->sopass[0]); in dp83822_set_wol()
159 (wol->sopass[3] << 8) | wol->sopass[2]); in dp83822_set_wol()
[all …]
/kernel/linux/linux-5.10/drivers/net/phy/
Dmarvell.c1 // SPDX-License-Identifier: GPL-2.0+
317 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) in marvell_config_intr()
369 err = marvell_set_polarity(phydev, phydev->mdix_ctrl); in marvell_config_aneg()
384 if (phydev->autoneg != AUTONEG_ENABLE || changed) { in marvell_config_aneg()
434 * marvell,reg-init property stored in the of_node for the phydev.
436 * marvell,reg-init = <reg-page reg mask value>,...;
438 * There may be one or more sets of <reg-page reg mask value>:
440 * reg-page: which register bank to use.
442 * mask: if non-zero, ANDed with existing register value.
451 if (!phydev->mdio.dev.of_node) in marvell_of_reg_init()
[all …]
Dlxt.c1 // SPDX-License-Identifier: GPL-2.0+
42 /* ------------------------------------------------------------------------- */
78 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) in lxt970_config_intr()
102 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) in lxt971_config_intr()
132 } while (status >= 0 && retry-- && status == control); in lxt973a2_update_link()
138 phydev->link = 0; in lxt973a2_update_link()
140 phydev->link = 1; in lxt973a2_update_link()
156 if (AUTONEG_ENABLE == phydev->autoneg) { in lxt973a2_read_status()
173 } while (lpa == adv && retry--); in lxt973a2_read_status()
175 mii_lpa_to_linkmode_lpa_t(phydev->lp_advertising, lpa); in lxt973a2_read_status()
[all …]
Ddp83822.c1 // SPDX-License-Identifier: GPL-2.0
101 /* SOR1 mode */
140 struct net_device *ndev = phydev->attached_dev; in dp83822_set_wol()
144 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) { in dp83822_set_wol()
145 mac = (const u8 *)ndev->dev_addr; in dp83822_set_wol()
148 return -EINVAL; in dp83822_set_wol()
162 if (wol->wolopts & WAKE_MAGIC) in dp83822_set_wol()
167 if (wol->wolopts & WAKE_MAGICSECURE) { in dp83822_set_wol()
170 (wol->sopass[1] << 8) | wol->sopass[0]); in dp83822_set_wol()
173 (wol->sopass[3] << 8) | wol->sopass[2]); in dp83822_set_wol()
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/intel/e1000/
De1000_param.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
12 #define OPTION_UNSET -1
30 * Valid Range: 80-256 for 82542 and 82543 gigabit ethernet controllers
31 * Valid Range: 80-4096 for 82544 and newer
39 * Valid Range: 80-256 for 82542 and 82543 gigabit ethernet controllers
40 * Valid Range: 80-4096 for 82544 and newer
49 * - 0 - auto-negotiate at all supported speeds
50 * - 10 - only link at 10 Mbps
51 * - 100 - only link at 100 Mbps
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/intel/e1000/
De1000_param.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
12 #define OPTION_UNSET -1
30 * Valid Range: 80-256 for 82542 and 82543 gigabit ethernet controllers
31 * Valid Range: 80-4096 for 82544 and newer
39 * Valid Range: 80-256 for 82542 and 82543 gigabit ethernet controllers
40 * Valid Range: 80-4096 for 82544 and newer
49 * - 0 - auto-negotiate at all supported speeds
50 * - 10 - only link at 10 Mbps
51 * - 100 - only link at 100 Mbps
[all …]
/kernel/linux/linux-6.6/drivers/net/hippi/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
11 1600Mbit/sec dual-simplex switched or point-to-point network. HIPPI
12 can run over copper (25m) or fiber (300m on multi-mode or 10km on
13 single-mode). HIPPI networks are commonly used for clusters and to
/kernel/linux/linux-5.10/drivers/net/hippi/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
11 1600Mbit/sec dual-simplex switched or point-to-point network. HIPPI
12 can run over copper (25m) or fiber (300m on multi-mode or 10km on
13 single-mode). HIPPI networks are commonly used for clusters and to
/kernel/linux/linux-5.10/drivers/net/
Dsungem_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * (c) 2002-2007, Benjamin Herrenscmidt (benh@kernel.crashing.org)
10 * - Add support for PHYs that provide an IRQ line
11 * - Eventually moved the entire polling state machine in
14 * - On LXT971 & BCM5201, Apple uses some chip specific regs
17 * - Apple has some additional power management code for some
53 return phy->mdio_read(phy->dev, id, reg); in __sungem_phy_read()
58 phy->mdio_write(phy->dev, id, reg, val); in __sungem_phy_write()
63 return phy->mdio_read(phy->dev, phy->mii_id, reg); in sungem_phy_read()
68 phy->mdio_write(phy->dev, phy->mii_id, reg, val); in sungem_phy_write()
[all …]
/kernel/linux/linux-6.6/drivers/net/
Dsungem_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * (c) 2002-2007, Benjamin Herrenscmidt (benh@kernel.crashing.org)
10 * - Add support for PHYs that provide an IRQ line
11 * - Eventually moved the entire polling state machine in
14 * - On LXT971 & BCM5201, Apple uses some chip specific regs
17 * - Apple has some additional power management code for some
49 return phy->mdio_read(phy->dev, id, reg); in __sungem_phy_read()
54 phy->mdio_write(phy->dev, id, reg, val); in __sungem_phy_write()
59 return phy->mdio_read(phy->dev, phy->mii_id, reg); in sungem_phy_read()
64 phy->mdio_write(phy->dev, phy->mii_id, reg, val); in sungem_phy_write()
[all …]
/kernel/linux/linux-6.6/Documentation/networking/device_drivers/ethernet/intel/
De1000e.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 2008-2018 Intel Corporation.
13 - Identifying Your Adapter
14 - Command Line Parameters
15 - Additional Configurations
16 - Support
48 ---------------------
49 :Valid Range: 0,1,3,4,100-100000
82 - 0: Off
86 - 1: Dynamic mode
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/intel/e1000e/
Dmac.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
7 * e1000e_get_bus_info_pcie - Get PCIe bus information
16 struct e1000_mac_info *mac = &hw->mac; in e1000e_get_bus_info_pcie()
17 struct e1000_bus_info *bus = &hw->bus; in e1000e_get_bus_info_pcie()
18 struct e1000_adapter *adapter = hw->adapter; in e1000e_get_bus_info_pcie()
21 cap_offset = adapter->pdev->pcie_cap; in e1000e_get_bus_info_pcie()
23 bus->width = e1000_bus_width_unknown; in e1000e_get_bus_info_pcie()
25 pci_read_config_word(adapter->pdev, in e1000e_get_bus_info_pcie()
28 bus->width = (enum e1000_bus_width)((pcie_link_status & in e1000e_get_bus_info_pcie()
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/intel/e1000e/
Dmac.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
7 * e1000e_get_bus_info_pcie - Get PCIe bus information
16 struct e1000_mac_info *mac = &hw->mac; in e1000e_get_bus_info_pcie()
17 struct e1000_bus_info *bus = &hw->bus; in e1000e_get_bus_info_pcie()
18 struct e1000_adapter *adapter = hw->adapter; in e1000e_get_bus_info_pcie()
21 cap_offset = adapter->pdev->pcie_cap; in e1000e_get_bus_info_pcie()
23 bus->width = e1000_bus_width_unknown; in e1000e_get_bus_info_pcie()
25 pci_read_config_word(adapter->pdev, in e1000e_get_bus_info_pcie()
28 bus->width = (enum e1000_bus_width)((pcie_link_status & in e1000e_get_bus_info_pcie()
[all …]
/kernel/linux/linux-5.10/Documentation/networking/device_drivers/ethernet/intel/
De1000e.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 2008-2018 Intel Corporation.
13 - Identifying Your Adapter
14 - Command Line Parameters
15 - Additional Configurations
16 - Support
48 ---------------------
49 :Valid Range: 0,1,3,4,100-100000
82 - 0: Off
86 - 1: Dynamic mode
[all …]
/kernel/linux/linux-5.10/drivers/net/dsa/microchip/
Dksz_common.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright (C) 2017-2019 Microchip Technology Inc.
36 u32 fiber:1; /* port is fiber */ member
158 void ksz_mac_link_down(struct dsa_switch *ds, int port, unsigned int mode,
184 int ret = regmap_read(dev->regmap[0], reg, &value); in ksz_read8()
193 int ret = regmap_read(dev->regmap[1], reg, &value); in ksz_read16()
202 int ret = regmap_read(dev->regmap[2], reg, &value); in ksz_read32()
213 ret = regmap_bulk_read(dev->regmap[2], reg, value, 2); in ksz_read64()
222 return regmap_write(dev->regmap[0], reg, value); in ksz_write8()
227 return regmap_write(dev->regmap[1], reg, value); in ksz_write16()
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/marvell/
Dsky2.h1 /* SPDX-License-Identifier: GPL-2.0 */
30 /* Yukon-2 */
32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
39 PCI_Y2_PME_LEGACY= 1<<15, /* PCI Express legacy power management mode */
[all …]

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