| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/can/ |
| D | xilinx,can.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
16 - xlnx,zynq-can-1.0
17 - xlnx,axi-can-1.00.a
18 - xlnx,canfd-1.0
19 - xlnx,canfd-2.0
31 clock-names:
34 power-domains:
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/can/ |
| D | xilinx_can.txt | 2 ---------------------------------------------------------
5 - compatible : Should be:
6 - "xlnx,zynq-can-1.0" for Zynq CAN controllers
7 - "xlnx,axi-can-1.00.a" for Axi CAN controllers
8 - "xlnx,canfd-1.0" for CAN FD controllers
9 - "xlnx,canfd-2.0" for CAN FD 2.0 controllers
10 - reg : Physical base address and size of the controller
12 - interrupts : Property with a value describing the interrupt
14 - clock-names : List of input clock names
15 - "can_clk", "pclk" (For CANPS),
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/ |
| D | altr,tse.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Maxime Chevallier <maxime.chevallier@bootlin.com>
15 - const: altr,tse-1.0
16 - const: ALTR,tse-1.0
18 - const: altr,tse-msgdma-1.0
23 interrupt-names:
25 - const: rx_irq
26 - const: tx_irq
[all …]
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| D | ti,dp83867.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Andrew Davis <afd@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
34 nvmem-cells:
40 nvmem-cell-names:
42 - const: io_impedance_ctrl
[all …]
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| D | ti,dp83869.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <afd@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
[all …]
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| D | adi,adin.yaml | 1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandru Tachici <alexandru.tachici@analog.com>
16 - $ref: ethernet-phy.yaml#
19 adi,rx-internal-delay-ps:
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
29 internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
33 adi,fifo-depth-bits:
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/ |
| D | altera_tse.txt | 1 * Altera Triple-Speed Ethernet MAC driver (TSE)
4 - compatible: Should be "altr,tse-1.0" for legacy SGDMA based TSE, and should
5 be "altr,tse-msgdma-1.0" for the preferred MSGDMA based TSE.
8 - reg: Address and length of the register set for the device. It contains
9 the information of registers in the same order as described by reg-names
10 - reg-names: Should contain the reg names
18 - interrupts: Should contain the TSE interrupts and it's mode.
19 - interrupt-names: Should contain the interrupt names
22 - rx-fifo-depth: MAC receive FIFO buffer depth in bytes
23 - tx-fifo-depth: MAC transmit FIFO buffer depth in bytes
[all …]
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| D | ti,dp83867.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - $ref: "ethernet-controller.yaml#"
14 - Dan Murphy <dmurphy@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
34 ti,min-output-impedance:
40 ti,max-output-impedance:
45 Note: ti,min-output-impedance and ti,max-output-impedance are mutually
[all …]
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| D | ti,dp83869.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - $ref: "ethernet-phy.yaml#"
14 - Dan Murphy <dmurphy@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
[all …]
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| D | adi,adin.yaml | 1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandru Ardelean <alexandru.ardelean@analog.com>
16 - $ref: ethernet-phy.yaml#
19 adi,rx-internal-delay-ps:
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
29 internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
33 adi,fifo-depth-bits:
[all …]
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| /kernel/linux/linux-6.6/drivers/staging/axis-fifo/ |
| D | axis-fifo.txt | 1 Xilinx AXI-Stream FIFO v4.1 IP core
3 This IP core has read and write AXI-Stream FIFOs, the contents of which can
4 be accessed from the AXI4 memory-mapped interface. This is useful for
11 Currently supports only store-forward mode with a 32-bit
12 AXI4-Lite interface. DOES NOT support:
13 - cut-through mode
14 - AXI4 (non-lite)
17 - compatible: Should be "xlnx,axi-fifo-mm-s-4.1"
18 - interrupt-names: Should be "interrupt"
19 - interrupt-parent: Should be <&intc>
[all …]
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| /kernel/linux/linux-5.10/drivers/staging/axis-fifo/ |
| D | axis-fifo.txt | 1 Xilinx AXI-Stream FIFO v4.1 IP core
3 This IP core has read and write AXI-Stream FIFOs, the contents of which can
4 be accessed from the AXI4 memory-mapped interface. This is useful for
11 Currently supports only store-forward mode with a 32-bit
12 AXI4-Lite interface. DOES NOT support:
13 - cut-through mode
14 - AXI4 (non-lite)
17 - compatible: Should be "xlnx,axi-fifo-mm-s-4.1"
18 - interrupt-names: Should be "interrupt"
19 - interrupt-parent: Should be <&intc>
[all …]
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| /kernel/linux/linux-5.10/sound/soc/meson/ |
| D | axg-fifo.c | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
14 #include <sound/soc-dai.h>
16 #include "axg-fifo.h"
20 * capture frontend DAI. The logic behind this two types of fifo is very
48 struct snd_soc_pcm_runtime *rtd = ss->private_data; in axg_fifo_dai()
64 return dai->dev; in axg_fifo_dev()
67 static void __dma_enable(struct axg_fifo *fifo, bool enable) in __dma_enable() argument
69 regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_DMA_EN, in __dma_enable()
76 struct axg_fifo *fifo = axg_fifo_data(ss); in axg_fifo_pcm_trigger() local
82 __dma_enable(fifo, true); in axg_fifo_pcm_trigger()
[all …]
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| /kernel/linux/linux-6.6/sound/soc/meson/ |
| D | axg-fifo.c | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
15 #include <sound/soc-dai.h>
17 #include "axg-fifo.h"
21 * capture frontend DAI. The logic behind this two types of fifo is very
49 struct snd_soc_pcm_runtime *rtd = ss->private_data; in axg_fifo_dai()
65 return dai->dev; in axg_fifo_dev()
68 static void __dma_enable(struct axg_fifo *fifo, bool enable) in __dma_enable() argument
70 regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_DMA_EN, in __dma_enable()
77 struct axg_fifo *fifo = axg_fifo_data(ss); in axg_fifo_pcm_trigger() local
83 __dma_enable(fifo, true); in axg_fifo_pcm_trigger()
[all …]
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| D | axg-frddr.c | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
17 #include <sound/soc-dai.h>
19 #include "axg-fifo.h"
38 struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai); in g12a_frddr_dai_prepare() local
41 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_frddr_dai_prepare()
43 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_frddr_dai_prepare()
45 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_frddr_dai_prepare()
55 struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai); in axg_frddr_dai_hw_params() local
56 unsigned int period, depth, val; in axg_frddr_dai_hw_params() local
60 /* Trim the FIFO depth if the period is small to improve latency */ in axg_frddr_dai_hw_params()
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/spi/ |
| D | cdns,qspi-nor.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vaishnav Achath <vaishnav.a@ti.com>
13 - $ref: spi-controller.yaml#
14 - if:
18 const: xlnx,versal-ospi-1.0
21 - power-domains
22 - if:
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/sound/ |
| D | amlogic,axg-fifo.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/amlogic,axg-fifo.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Amlogic AXG Audio FIFO controllers
10 - Jerome Brunet <jbrunet@baylibre.com>
15 - enum:
16 - amlogic,axg-toddr
17 - amlogic,axg-frddr
18 - items:
[all …]
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| /kernel/linux/linux-6.6/include/linux/soc/qcom/ |
| D | geni-se.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
15 * @GENI_SE_FIFO: FIFO mode. Data is transferred with SE FIFO
56 * struct geni_se - GENI Serial Engine
258 * For QUP HW Version >= 3.10 Tx fifo depth support is increased
269 * For QUP HW Version >= 3.10 Rx fifo depth support is increased
309 * geni_se_read_proto() - Read the protocol configured for a serial engine
318 val = readl_relaxed(se->base + GENI_FW_REVISION_RO); in geni_se_read_proto()
324 * geni_se_setup_m_cmd() - Setup the primary sequencer
337 writel(m_cmd, se->base + SE_GENI_M_CMD0); in geni_se_setup_m_cmd()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/ |
| D | amlogic,axg-fifo.txt | 1 * Amlogic Audio FIFO controllers
4 - compatible: 'amlogic,axg-toddr' or
5 'amlogic,axg-toddr' or
6 'amlogic,g12a-frddr' or
7 'amlogic,g12a-toddr' or
8 'amlogic,sm1-frddr' or
9 'amlogic,sm1-toddr'
10 - reg: physical base address of the controller and length of memory
12 - interrupts: interrupt specifier for the fifo.
13 - clocks: phandle to the fifo peripheral clock provided by the audio
[all …]
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| /kernel/linux/linux-6.6/Documentation/networking/device_drivers/can/freescale/ |
| D | flexcan.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
7 Authors: Marc Kleine-Budde <mkl@pengutronix.de>,
15 - FIFO
16 - mailbox
20 configured for RX-FIFO mode.
22 The RX FIFO mode uses a hardware FIFO with a depth of 6 CAN frames,
23 while the mailbox mode uses a software FIFO with a depth of up to 62
30 With the "rx-rtr" private flag the ability to receive RTR frames can
34 "rx-rtr" on
40 more performant "RX mailbox" mode and will use "RX FIFO" mode
[all …]
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| /kernel/linux/linux-5.10/include/linux/ |
| D | qcom-geni-se.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
42 * struct geni_se - GENI Serial Engine
274 * geni_se_read_proto() - Read the protocol configured for a serial engine
283 val = readl_relaxed(se->base + GENI_FW_REVISION_RO); in geni_se_read_proto()
289 * geni_se_setup_m_cmd() - Setup the primary sequencer
302 writel(m_cmd, se->base + SE_GENI_M_CMD0); in geni_se_setup_m_cmd()
306 * geni_se_setup_s_cmd() - Setup the secondary sequencer
318 s_cmd = readl_relaxed(se->base + SE_GENI_S_CMD0); in geni_se_setup_s_cmd()
322 writel(s_cmd, se->base + SE_GENI_S_CMD0); in geni_se_setup_s_cmd()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/ |
| D | cadence-quadspi.txt | 4 - compatible : should be one of the following:
5 Generic default - "cdns,qspi-nor".
6 For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
7 For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor".
8 - reg : Contains two entries, each of which is a tuple consisting of a
12 - interrupts : Unit interrupt specifier for the controller interrupt.
13 - clocks : phandle to the Quad SPI clock.
14 - cdns,fifo-depth : Size of the data FIFO in words.
15 - cdns,fifo-width : Bus width of the data FIFO in bytes.
16 - cdns,trigger-address : 32-bit indirect AHB trigger address.
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/amlogic/ |
| D | meson-sm1.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-g12-common.dtsi"
8 #include <dt-bindings/clock/axg-audio-clkc.h>
9 #include <dt-bindings/power/meson-sm1-power.h>
10 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
11 #include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h>
16 tdmif_a: audio-controller-0 {
17 compatible = "amlogic,axg-tdm-iface";
18 #sound-dai-cells = <0>;
19 sound-name-prefix = "TDM_A";
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/i2c/ |
| D | cdns,i2c-r1p10.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/cdns,i2c-r1p10.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
18 - cdns,i2c-r1p10 # cadence i2c controller version 1.0
19 - cdns,i2c-r1p14 # cadence i2c controller version 1.4
33 clock-frequency:
39 clock-name:
[all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/amlogic/ |
| D | meson-sm1.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-g12-common.dtsi"
8 #include <dt-bindings/clock/axg-audio-clkc.h>
9 #include <dt-bindings/power/meson-sm1-power.h>
10 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
11 #include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h>
16 tdmif_a: audio-controller-0 {
17 compatible = "amlogic,axg-tdm-iface";
18 #sound-dai-cells = <0>;
19 sound-name-prefix = "TDM_A";
[all …]
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