| /kernel/linux/linux-6.6/drivers/staging/axis-fifo/ |
| D | axis-fifo.txt | 1 Xilinx AXI-Stream FIFO v4.1 IP core
3 This IP core has read and write AXI-Stream FIFOs, the contents of which can
4 be accessed from the AXI4 memory-mapped interface. This is useful for
11 Currently supports only store-forward mode with a 32-bit
12 AXI4-Lite interface. DOES NOT support:
13 - cut-through mode
14 - AXI4 (non-lite)
17 - compatible: Should be "xlnx,axi-fifo-mm-s-4.1"
18 - interrupt-names: Should be "interrupt"
19 - interrupt-parent: Should be <&intc>
[all …]
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| D | axis-fifo.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx AXIS FIFO: interface to the Xilinx AXI-Stream FIFO IP core
12 /* ----------------------------
14 * ----------------------------
37 /* ----------------------------
39 * ----------------------------
47 /* ----------------------------
49 * ----------------------------
68 /* ----------------------------
70 * ----------------------------
[all …]
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| /kernel/linux/linux-5.10/drivers/staging/axis-fifo/ |
| D | axis-fifo.txt | 1 Xilinx AXI-Stream FIFO v4.1 IP core
3 This IP core has read and write AXI-Stream FIFOs, the contents of which can
4 be accessed from the AXI4 memory-mapped interface. This is useful for
11 Currently supports only store-forward mode with a 32-bit
12 AXI4-Lite interface. DOES NOT support:
13 - cut-through mode
14 - AXI4 (non-lite)
17 - compatible: Should be "xlnx,axi-fifo-mm-s-4.1"
18 - interrupt-names: Should be "interrupt"
19 - interrupt-parent: Should be <&intc>
[all …]
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| D | axis-fifo.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx AXIS FIFO: interface to the Xilinx AXI-Stream FIFO IP core
12 /* ----------------------------
14 * ----------------------------
38 /* ----------------------------
40 * ----------------------------
48 /* ----------------------------
50 * ----------------------------
69 /* ----------------------------
71 * ----------------------------
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/spi/ |
| D | cdns,qspi-nor.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vaishnav Achath <vaishnav.a@ti.com>
13 - $ref: spi-controller.yaml#
14 - if:
18 const: xlnx,versal-ospi-1.0
21 - power-domains
22 - if:
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/ |
| D | cadence-quadspi.txt | 4 - compatible : should be one of the following:
5 Generic default - "cdns,qspi-nor".
6 For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
7 For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor".
8 - reg : Contains two entries, each of which is a tuple consisting of a
12 - interrupts : Unit interrupt specifier for the controller interrupt.
13 - clocks : phandle to the Quad SPI clock.
14 - cdns,fifo-depth : Size of the data FIFO in words.
15 - cdns,fifo-width : Bus width of the data FIFO in bytes.
16 - cdns,trigger-address : 32-bit indirect AHB trigger address.
[all …]
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| /kernel/linux/linux-6.6/drivers/staging/media/atomisp/pci/ |
| D | ia_css_stream_public.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
36 IA_CSS_INPUT_MODE_FIFO, /** data from input-fifo */
37 IA_CSS_INPUT_MODE_TPG, /** data from test-pattern generator */
38 IA_CSS_INPUT_MODE_PRBS, /** data from pseudo-random bit stream */
69 int linked_isys_stream_id; /** default value is -1, other value means
127 s32 flash_gpio_pin; /** pin on which the flash is connected, -1 for no flash */
128 int left_padding; /** The number of input-formatter left-paddings, -1 for default from binary.*/
158 stream_config->online = true;
159 stream_config->left_padding = -1;
266 * @param[in] output_padded_width - the output buffer stride.
[all …]
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| /kernel/linux/linux-5.10/drivers/staging/media/atomisp/pci/ |
| D | ia_css_stream_public.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
36 IA_CSS_INPUT_MODE_FIFO, /** data from input-fifo */
37 IA_CSS_INPUT_MODE_TPG, /** data from test-pattern generator */
38 IA_CSS_INPUT_MODE_PRBS, /** data from pseudo-random bit stream */
69 int linked_isys_stream_id; /** default value is -1, other value means
129 s32 flash_gpio_pin; /** pin on which the flash is connected, -1 for no flash */
130 int left_padding; /** The number of input-formatter left-paddings, -1 for default from binary.*/
160 stream_config->online = true;
161 stream_config->left_padding = -1;
277 * @param[in] output_padded_width - the output buffer stride.
[all …]
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| /kernel/linux/linux-6.6/include/video/ |
| D | s1d13xxxfb.h | 4 * (c) 2005 Thibaut VARENE <varenet@parisc-linux.org>
44 #define S1DREG_LCD_DISP_HWIDTH 0x0032 /* LCD Horizontal Display Width Register: ((val)+1)*8)=pix/l…
45 #define S1DREG_LCD_NDISP_HPER 0x0034 /* LCD Horizontal Non-Display Period Register: ((val)+1)*8)=N…
47 #define S1DREG_TFT_FPLINE_PWIDTH 0x0036 /* TFT FPLINE Pulse Width Register. */
50 #define S1DREG_LCD_NDISP_VPER 0x003A /* LCD Vertical Non-Display Period Register: (val)+1=NDlines …
52 #define S1DREG_TFT_FPFRAME_PWIDTH 0x003C /* TFT FPFRAME Pulse Width Register */
61 #define S1DREG_LCD_DISP_FIFO_HTC 0x004A /* LCD Display FIFO High Threshold Control Register */
62 #define S1DREG_LCD_DISP_FIFO_LTC 0x004B /* LCD Display FIFO Low Threshold Control Register */
63 #define S1DREG_CRT_DISP_HWIDTH 0x0050 /* CRT/TV Horizontal Display Width Register: ((val)+1)*8)=pi…
64 #define S1DREG_CRT_NDISP_HPER 0x0052 /* CRT/TV Horizontal Non-Display Period Register */
[all …]
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| /kernel/linux/linux-5.10/include/video/ |
| D | s1d13xxxfb.h | 4 * (c) 2005 Thibaut VARENE <varenet@parisc-linux.org>
44 #define S1DREG_LCD_DISP_HWIDTH 0x0032 /* LCD Horizontal Display Width Register: ((val)+1)*8)=pix/l…
45 #define S1DREG_LCD_NDISP_HPER 0x0034 /* LCD Horizontal Non-Display Period Register: ((val)+1)*8)=N…
47 #define S1DREG_TFT_FPLINE_PWIDTH 0x0036 /* TFT FPLINE Pulse Width Register. */
50 #define S1DREG_LCD_NDISP_VPER 0x003A /* LCD Vertical Non-Display Period Register: (val)+1=NDlines …
52 #define S1DREG_TFT_FPFRAME_PWIDTH 0x003C /* TFT FPFRAME Pulse Width Register */
61 #define S1DREG_LCD_DISP_FIFO_HTC 0x004A /* LCD Display FIFO High Threshold Control Register */
62 #define S1DREG_LCD_DISP_FIFO_LTC 0x004B /* LCD Display FIFO Low Threshold Control Register */
63 #define S1DREG_CRT_DISP_HWIDTH 0x0050 /* CRT/TV Horizontal Display Width Register: ((val)+1)*8)=pi…
64 #define S1DREG_CRT_NDISP_HPER 0x0052 /* CRT/TV Horizontal Non-Display Period Register */
[all …]
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| /kernel/linux/linux-5.10/drivers/usb/dwc2/ |
| D | params.c | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) 2004-2016 Synopsys, Inc.
14 * 3. The names of the above-listed copyright holders may not be used
44 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_bcm_params()
46 p->host_rx_fifo_size = 774; in dwc2_set_bcm_params()
47 p->max_transfer_size = 65535; in dwc2_set_bcm_params()
48 p->max_packet_count = 511; in dwc2_set_bcm_params()
49 p->ahbcfg = 0x10; in dwc2_set_bcm_params()
54 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_his_params()
56 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; in dwc2_set_his_params()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/vmwgfx/device_include/ |
| D | svga_reg.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
3 * Copyright 1998-2015 VMware, Inc.
28 * svga_reg.h --
72 * Legal values for the SVGA_REG_CURSOR_ON register in old-fashioned
133 #define SVGA_IRQFLAG_FIFO_PROGRESS 0x2 /* Made forward progress in the FIFO */
139 * The byte-size is the size of the actual cursor data,
142 * 40K is sufficient memory for two 32-bit planes for a 64 x 64 cursor.
144 * The dimension limit is a bound on the maximum width or height.
179 SVGA_REG_SYNC = 21, /* See "FIFO Synchronization Registers" */
180 SVGA_REG_BUSY = 22, /* See "FIFO Synchronization Registers" */
[all …]
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| /kernel/linux/linux-5.10/drivers/media/i2c/cx25840/ |
| D | cx25840-ir.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <media/drv-intf/cx25840.h>
14 #include <media/rc-core.h>
16 #include "cx25840-core.h"
117 return state ? state->ir_state : NULL; in to_ir_state()
135 d--; in count_to_clock_divider()
213 * FIFO register pulse width count computations
219 * of the pulse width counter as read from the FIFO. The two lsb's are in clock_divider_to_resolution()
232 * The 2 lsb's of the pulse width timer count are not readable, hence in pulse_width_count_to_ns()
251 * The 2 lsb's of the pulse width timer count are not accessible, hence
[all …]
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| /kernel/linux/linux-6.6/drivers/media/i2c/cx25840/ |
| D | cx25840-ir.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <media/drv-intf/cx25840.h>
14 #include <media/rc-core.h>
16 #include "cx25840-core.h"
117 return state ? state->ir_state : NULL; in to_ir_state()
135 d--; in count_to_clock_divider()
193 * FIFO register pulse width count computations
199 * the pulse width counter as read from the FIFO. The two lsb's are in clock_divider_to_resolution()
212 * The 2 lsb's of the pulse width timer count are not readable, hence in pulse_width_count_to_ns()
231 * The 2 lsb's of the pulse width timer count are not accessible, hence
[all …]
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| /kernel/linux/linux-6.6/drivers/usb/dwc2/ |
| D | params.c | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) 2004-2016 Synopsys, Inc.
20 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_bcm_params()
22 p->host_rx_fifo_size = 774; in dwc2_set_bcm_params()
23 p->max_transfer_size = 65535; in dwc2_set_bcm_params()
24 p->max_packet_count = 511; in dwc2_set_bcm_params()
25 p->ahbcfg = 0x10; in dwc2_set_bcm_params()
30 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_his_params()
32 p->otg_caps.hnp_support = false; in dwc2_set_his_params()
33 p->otg_caps.srp_support = false; in dwc2_set_his_params()
[all …]
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| /kernel/linux/linux-5.10/sound/soc/meson/ |
| D | axg-toddr.c | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
14 #include <sound/soc-dai.h>
16 #include "axg-fifo.h"
42 struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai); in g12a_toddr_dai_prepare() local
45 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_toddr_dai_prepare()
47 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_toddr_dai_prepare()
49 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_toddr_dai_prepare()
59 struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai); in axg_toddr_dai_hw_params() local
60 unsigned int type, width; in axg_toddr_dai_hw_params() local
67 type = 2; /* 4 samples of 16 bits - right justified */ in axg_toddr_dai_hw_params()
[all …]
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| /kernel/linux/linux-6.6/sound/soc/meson/ |
| D | axg-toddr.c | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
15 #include <sound/soc-dai.h>
17 #include "axg-fifo.h"
40 struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai); in g12a_toddr_dai_prepare() local
43 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_toddr_dai_prepare()
45 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_toddr_dai_prepare()
47 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_toddr_dai_prepare()
57 struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai); in axg_toddr_dai_hw_params() local
58 unsigned int type, width; in axg_toddr_dai_hw_params() local
65 type = 2; /* 4 samples of 16 bits - right justified */ in axg_toddr_dai_hw_params()
[all …]
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| /kernel/linux/linux-6.6/drivers/media/rc/ |
| D | ite-cir.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 #define ITE_DRIVER_NAME "ite-cir"
11 /* FIFO sizes */
34 /* hw-specific operation function pointers; most of these must be
35 * called while holding the spin lock, except for the TX FIFO length
50 /* read bytes from RX FIFO; return read count */
53 /* enable tx FIFO space available interrupt */
56 /* disable tx FIFO space available interrupt */
59 /* get number of full TX FIFO slots */
62 /* put a byte to the TX FIFO */
[all …]
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| /kernel/linux/linux-5.10/drivers/media/rc/ |
| D | ite-cir.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 #define ITE_DRIVER_NAME "ite-cir"
26 /* FIFO sizes */
64 /* duty cycle, 0-100 */
67 /* hw-specific operation function pointers; most of these must be
68 * called while holding the spin lock, except for the TX FIFO length
83 /* read bytes from RX FIFO; return read count */
86 /* enable tx FIFO space available interrupt */
89 /* disable tx FIFO space available interrupt */
92 /* get number of full TX FIFO slots */
[all …]
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| /kernel/linux/linux-5.10/drivers/video/fbdev/riva/ |
| D | riva_hw.c | 3 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
7 |* hereby granted a nonexclusive, royalty-free copyright license to *|
10 |* Any use of this source code must include, in the user documenta- *|
14 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
18 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
20 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
22 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
32 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
34 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
[all …]
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| /kernel/linux/linux-5.10/drivers/i2c/busses/ |
| D | i2c-st.c | 1 // SPDX-License-Identifier: GPL-2.0-only
103 /* SSC Tx FIFO Status */
106 /* SSC Rx FIFO Status */
130 * struct st_i2c_timings - per-Mode tuning parameters
138 * @sda_pulse_min_limit: I2C SDA pulse mini width limit
152 * struct st_i2c_client - client specific data
153 * @addr: 8-bit slave addr, including r/w bit
170 * struct st_i2c_dev - private data of the controller
178 * @scl_min_width_us: SCL line minimum pulse width in us
179 * @sda_min_width_us: SDA line minimum pulse width in us
[all …]
|
| /kernel/linux/linux-6.6/drivers/i2c/busses/ |
| D | i2c-st.c | 1 // SPDX-License-Identifier: GPL-2.0-only
103 /* SSC Tx FIFO Status */
106 /* SSC Rx FIFO Status */
130 * struct st_i2c_timings - per-Mode tuning parameters
138 * @sda_pulse_min_limit: I2C SDA pulse mini width limit
152 * struct st_i2c_client - client specific data
153 * @addr: 8-bit slave addr, including r/w bit
170 * struct st_i2c_dev - private data of the controller
178 * @scl_min_width_us: SCL line minimum pulse width in us
179 * @sda_min_width_us: SDA line minimum pulse width in us
[all …]
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| /kernel/linux/linux-6.6/drivers/media/pci/cx23885/ |
| D | cx23888-ir.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include "cx23888-ir.h"
16 #include <media/v4l2-device.h>
17 #include <media/rc-core.h>
174 d--; in count_to_clock_divider()
232 * FIFO register pulse width count computations
238 * the pulse width counter as read from the FIFO. The two lsb's are in clock_divider_to_resolution()
251 * The 2 lsb's of the pulse width timer count are not readable, hence in pulse_width_count_to_ns()
267 * The 2 lsb's of the pulse width timer count are not readable, hence in pulse_width_count_to_us()
278 * Pulse Clocks computations: Combined Pulse Width Count & Rx Clock Counts
[all …]
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| /kernel/linux/linux-5.10/drivers/media/pci/cx23885/ |
| D | cx23888-ir.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include "cx23888-ir.h"
16 #include <media/v4l2-device.h>
17 #include <media/rc-core.h>
174 d--; in count_to_clock_divider()
232 * FIFO register pulse width count computations
238 * of the pulse width counter as read from the FIFO. The two lsb's are in clock_divider_to_resolution()
251 * The 2 lsb's of the pulse width timer count are not readable, hence in pulse_width_count_to_ns()
267 * The 2 lsb's of the pulse width timer count are not readable, hence in pulse_width_count_to_us()
278 * Pulse Clocks computations: Combined Pulse Width Count & Rx Clock Counts
[all …]
|
| /kernel/linux/linux-6.6/drivers/video/fbdev/riva/ |
| D | riva_hw.c | 3 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
7 |* hereby granted a nonexclusive, royalty-free copyright license to *|
10 |* Any use of this source code must include, in the user documenta- *|
14 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
18 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
20 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
22 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
32 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
34 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
[all …]
|