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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dfixed-mmio-clock.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fixed-mmio-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple memory mapped IO fixed-rate clock sources
10 This binding describes a fixed-rate clock for which the frequency can
11 be read from a single 32-bit memory mapped I/O register.
17 - Jan Kotas <jank@cadence.com>
21 const: fixed-mmio-clock
26 "#clock-cells":
[all …]
/kernel/linux/linux-5.10/drivers/phy/hisilicon/
Dphy-histb-combphy.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016-2017 HiSilicon Co., Ltd. http://www.hisilicon.com
20 #include <dt-bindings/phy/phy.h>
36 int fixed; member
44 void __iomem *mmio; member
55 void __iomem *reg = priv->mmio + COMBPHY_CFG_REG; in nano_register_write()
75 return (mode->fixed != PHY_NONE) ? true : false; in is_mode_fixed()
80 struct histb_combphy_mode *mode = &priv->mode; in histb_combphy_set_mode()
81 struct regmap *syscon = priv->syscon; in histb_combphy_set_mode()
87 switch (mode->select) { in histb_combphy_set_mode()
[all …]
/kernel/linux/linux-6.6/drivers/phy/hisilicon/
Dphy-histb-combphy.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016-2017 HiSilicon Co., Ltd. http://www.hisilicon.com
21 #include <dt-bindings/phy/phy.h>
37 int fixed; member
45 void __iomem *mmio; member
56 void __iomem *reg = priv->mmio + COMBPHY_CFG_REG; in nano_register_write()
76 return (mode->fixed != PHY_NONE) ? true : false; in is_mode_fixed()
81 struct histb_combphy_mode *mode = &priv->mode; in histb_combphy_set_mode()
82 struct regmap *syscon = priv->syscon; in histb_combphy_set_mode()
88 switch (mode->select) { in histb_combphy_set_mode()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dfixed-mmio-clock.txt1 Binding for simple memory mapped io fixed-rate clock sources.
2 The driver reads a clock frequency value from a single 32-bit memory mapped
3 I/O register and registers it as a fixed rate clock.
7 This binding uses the common clock binding[1].
9 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - compatible : shall be "fixed-mmio-clock".
13 - #clock-cells : from common clock binding; shall be set to 0.
14 - reg : Address and length of the clock value register set.
17 - clock-output-names : From common clock binding.
21 #clock-cells = <0>;
[all …]
/kernel/linux/linux-5.10/drivers/clk/
Dclk-fixed-mmio.c1 // SPDX-License-Identifier: GPL-2.0
4 * Memory Mapped IO Fixed clock driver
12 #include <linux/clk-provider.h>
21 const char *clk_name = node->name; in fixed_mmio_clk_setup()
29 return ERR_PTR(-EIO); in fixed_mmio_clk_setup()
34 of_property_read_string(node, "clock-output-names", &clk_name); in fixed_mmio_clk_setup()
38 pr_err("%pOFn: failed to register fixed rate clock\n", node); in fixed_mmio_clk_setup()
44 pr_err("%pOFn: failed to add clock provider\n", node); in fixed_mmio_clk_setup()
56 CLK_OF_DECLARE(fixed_mmio_clk, "fixed-mmio-clock", of_fixed_mmio_clk_setup);
65 clk = fixed_mmio_clk_setup(pdev->dev.of_node); in of_fixed_mmio_clk_probe()
[all …]
/kernel/linux/linux-6.6/drivers/clk/
Dclk-fixed-mmio.c1 // SPDX-License-Identifier: GPL-2.0
4 * Memory Mapped IO Fixed clock driver
12 #include <linux/clk-provider.h>
21 const char *clk_name = node->name; in fixed_mmio_clk_setup()
29 return ERR_PTR(-EIO); in fixed_mmio_clk_setup()
34 of_property_read_string(node, "clock-output-names", &clk_name); in fixed_mmio_clk_setup()
38 pr_err("%pOFn: failed to register fixed rate clock\n", node); in fixed_mmio_clk_setup()
44 pr_err("%pOFn: failed to add clock provider\n", node); in fixed_mmio_clk_setup()
56 CLK_OF_DECLARE(fixed_mmio_clk, "fixed-mmio-clock", of_fixed_mmio_clk_setup);
65 clk = fixed_mmio_clk_setup(pdev->dev.of_node); in of_fixed_mmio_clk_probe()
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/kernel/linux/linux-6.6/arch/arc/boot/dts/
Dhaps_hs.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com)
5 /dts-v1/;
12 #address-cells = <2>;
13 #size-cells = <2>;
14 interrupt-parent = <&core_intc>;
24 … "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
32 compatible = "simple-bus";
33 #address-cells = <1>;
34 #size-cells = <1>;
[all …]
/kernel/linux/linux-5.10/arch/arc/boot/dts/
Dhaps_hs.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com)
5 /dts-v1/;
12 #address-cells = <2>;
13 #size-cells = <2>;
14 interrupt-parent = <&core_intc>;
24 … "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
32 compatible = "simple-bus";
33 #address-cells = <1>;
34 #size-cells = <1>;
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/marvell/
Darmada-xp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
16 #include "armada-370-xp.dtsi"
19 #address-cells = <2>;
20 #size-cells = <2>;
23 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
31 compatible = "marvell,armadaxp-mbus", "simple-bus";
38 internal-regs {
40 compatible = "marvell,armada-xp-sdram-controller";
[all …]
Darmada-38x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
32 compatible = "arm,cortex-a9-pmu";
33 interrupts-extended = <&mpic 3>;
37 compatible = "marvell,armada380-mbus", "simple-bus";
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Darmada-xp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
16 #include "armada-370-xp.dtsi"
19 #address-cells = <2>;
20 #size-cells = <2>;
23 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
31 compatible = "marvell,armadaxp-mbus", "simple-bus";
38 internal-regs {
40 compatible = "marvell,armada-xp-sdram-controller";
[all …]
Dsuniv-f1c100s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
8 #address-cells = <1>;
9 #size-cells = <1>;
10 interrupt-parent = <&intc>;
13 osc24M: clk-24M {
14 #clock-cells = <0>;
15 compatible = "fixed-clock";
16 clock-frequency = <24000000>;
17 clock-output-names = "osc24M";
20 osc32k: clk-32k {
[all …]
Darmada-38x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
32 compatible = "arm,cortex-a9-pmu";
33 interrupts-extended = <&mpic 3>;
37 compatible = "marvell,armada380-mbus", "simple-bus";
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/calxeda/
Dhb-sregs.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/calxeda/hb-sregs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The Calxeda Highbank system has a block of MMIO registers controlling
15 - Andre Przywara <andre.przywara@arm.com>
19 const: calxeda,hb-sregs
28 - compatible
29 - reg
34 - |
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/calxeda/
Dhb-sregs.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/calxeda/hb-sregs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The Calxeda Highbank system has a block of MMIO registers controlling
15 - Andre Przywara <andre.przywara@arm.com>
19 const: calxeda,hb-sregs
28 - compatible
29 - reg
34 - |
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/sigmastar/
Dmstar-v7.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/mstar-msc313-mpll.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
14 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a7";
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/nspire/
Dnspire.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #address-cells = <1>;
8 #size-cells = <1>;
9 interrupt-parent = <&intc>;
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,arm926ej-s";
27 compatible = "mmio-sram";
29 #address-cells = <1>;
30 #size-cells = <1>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/
Dqcom_nandc.txt4 - compatible: must be one of the following:
5 * "qcom,ipq806x-nand" - for EBI2 NAND controller being used in IPQ806x
7 * "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in
9 * "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in
12 - reg: MMIO address range
13 - clocks: must contain core clock and always on clock
14 - clock-names: must contain "core" for the core clock and "aon" for the
15 always on clock
18 - dmas: DMA specifier, consisting of a phandle to the ADM DMA
21 - dma-names: must be "rxtx"
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/arm/
Drtsm_ve-motherboard.dtsi1 // SPDX-License-Identifier: GPL-2.0
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <24000000>;
15 clock-output-names = "v2m:clk24mhz";
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
21 clock-frequency = <1000000>;
22 clock-output-names = "v2m:refclk1mhz";
26 compatible = "fixed-clock";
[all …]
Dfoundation-v8.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 model = "Foundation-v8A";
16 compatible = "arm,foundation-aarch64", "arm,vexpress";
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
31 #address-cells = <2>;
32 #size-cells = <0>;
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/arm/
Drtsm_ve-motherboard.dtsi1 // SPDX-License-Identifier: GPL-2.0
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <24000000>;
15 clock-output-names = "v2m:clk24mhz";
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
21 clock-frequency = <1000000>;
22 clock-output-names = "v2m:refclk1mhz";
26 compatible = "fixed-clock";
[all …]
Dfoundation-v8.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 model = "Foundation-v8A";
16 compatible = "arm,foundation-aarch64", "arm,vexpress";
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
31 #address-cells = <2>;
32 #size-cells = <0>;
[all …]
/kernel/linux/linux-6.6/drivers/interconnect/qcom/
Dicc-rpm.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/interconnect-provider.h>
16 #include "icc-common.h"
17 #include "icc-rpm.h"
55 struct icc_provider *provider = src->provider; in qcom_icc_set_qnoc_qos()
57 struct qcom_icc_node *qn = src->data; in qcom_icc_set_qnoc_qos()
58 struct qcom_icc_qos *qos = &qn->qos; in qcom_icc_set_qnoc_qos()
61 rc = regmap_update_bits(qp->regmap, in qcom_icc_set_qnoc_qos()
62 qp->qos_offset + QNOC_QOS_MCTL_LOWn_ADDR(qos->qos_port), in qcom_icc_set_qnoc_qos()
64 qos->areq_prio << QNOC_QOS_MCTL_DFLT_PRIO_SHIFT); in qcom_icc_set_qnoc_qos()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/dsi/pll/
Ddsi_pll_14nm.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
13 * DSI PLL 14nm - clock diagram (eg: DSI0):
18 * +----+ | +----+
19 * dsi0vco_clk ---| n1 |--o--| /8 |-- dsi0pllbyte
20 * +----+ | +----+
22 * | +----+ |
23 * o---| /2 |--o--|\
24 * | +----+ | \ +----+
25 * | | |--| n2 |-- dsi0pll
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/microchip/
Dsparx5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/microchip,sparx5.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <1>;
23 stdout-path = "serial0:115200n8";
27 #address-cells = <2>;
28 #size-cells = <0>;
[all …]

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