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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dsmsc911x.txt1 * Smart Mixed-Signal Connectivity (SMSC) LAN911x/912x Controller
4 - compatible : Should be "smsc,lan<model>", "smsc,lan9115"
5 - reg : Address and length of the io space for SMSC LAN
6 - interrupts : one or two interrupt specifiers
7 - The first interrupt is the SMSC LAN interrupt line
8 - The second interrupt (if present) is the PME (power
11 - phy-mode : See ethernet.txt file in the same directory
14 - reg-shift : Specify the quantity to shift the register offsets by
15 - reg-io-width : Specify the size (in bytes) of the IO accesses that
18 - smsc,irq-active-high : Indicates the IRQ polarity is active-high
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Dsmsc,lan9115.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Smart Mixed-Signal Connectivity (SMSC) LAN911x/912x Controller
10 - Shawn Guo <shawnguo@kernel.org>
13 - $ref: ethernet-controller.yaml#
18 - const: smsc,lan9115
19 - items:
20 - enum:
21 - smsc,lan89218
[all …]
/kernel/linux/linux-5.10/Documentation/networking/device_drivers/ethernet/davicom/
Ddm9000.rst1 .. SPDX-License-Identifier: GPL-2.0
9 Ben Dooks <ben@simtec.co.uk> <ben-linux@fluff.org>
13 ------------
15 This file describes how to use the DM9000 platform-device based network driver
25 ----------------------------
37 An example from arch/arm/mach-s3c2410/mach-bast.c is::
91 -------------
94 device, whether or not an external PHY is attached to the device and
113 The chip is connected to an external PHY.
122 Switch to using the simpler PHY polling method which does not
[all …]
/kernel/linux/linux-6.6/Documentation/networking/device_drivers/ethernet/davicom/
Ddm9000.rst1 .. SPDX-License-Identifier: GPL-2.0
9 Ben Dooks <ben@simtec.co.uk> <ben-linux@fluff.org>
13 ------------
15 This file describes how to use the DM9000 platform-device based network driver
25 ----------------------------
37 An example from arch/arm/mach-s3c/mach-bast.c is::
91 -------------
94 device, whether or not an external PHY is attached to the device and
113 The chip is connected to an external PHY.
122 Switch to using the simpler PHY polling method which does not
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-omap2/
Domap_phy_internal.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * This file configures the internal USB PHY in OMAP4430. Used
6 * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com
28 * omap4430_phy_power_down: disable MUSB PHY during early init
30 * OMAP4 MUSB PHY module is enabled by default on reset, but this will
44 return -ENOMEM; in omap4430_phy_power_down()
47 /* Power down the phy */ in omap4430_phy_power_down()
79 * Start the on-chip PHY and its PLL. in am35x_musb_phy_power()
88 pr_info("Waiting for PHY clock good...\n"); in am35x_musb_phy_power()
94 pr_err("musb PHY clock good timed out\n"); in am35x_musb_phy_power()
[all …]
/kernel/linux/linux-5.10/arch/mips/include/asm/mach-bcm63xx/
Dbcm63xx_dev_enet.h1 /* SPDX-License-Identifier: GPL-2.0 */
21 /* or fill phy info to use an external one */
26 /* if has_phy, use autonegotiated pause parameters or force
50 /* DMA engine has internal SRAM */
68 #define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */
69 #define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */
98 /* DMA engine has internal SRAM */
/kernel/linux/linux-6.6/arch/mips/include/asm/mach-bcm63xx/
Dbcm63xx_dev_enet.h1 /* SPDX-License-Identifier: GPL-2.0 */
21 /* or fill phy info to use an external one */
26 /* if has_phy, use autonegotiated pause parameters or force
50 /* DMA engine has internal SRAM */
68 #define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */
69 #define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */
98 /* DMA engine has internal SRAM */
/kernel/linux/linux-5.10/drivers/net/ethernet/intel/ixgbe/
Dixgbe_x550.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
17 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_get_invariants_X550_x()
18 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_get_invariants_X550_x() local
19 struct ixgbe_link_info *link = &hw->link; in ixgbe_get_invariants_X550_x()
24 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) in ixgbe_get_invariants_X550_x()
25 phy->ops.set_phy_power = NULL; in ixgbe_get_invariants_X550_x()
27 link->addr = IXGBE_CS4227; in ixgbe_get_invariants_X550_x()
34 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_get_invariants_X550_x_fw() local
39 phy->ops.set_phy_power = NULL; in ixgbe_get_invariants_X550_x_fw()
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/intel/ixgbe/
Dixgbe_x550.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
17 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_get_invariants_X550_x()
18 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_get_invariants_X550_x() local
19 struct ixgbe_link_info *link = &hw->link; in ixgbe_get_invariants_X550_x()
24 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) in ixgbe_get_invariants_X550_x()
25 phy->ops.set_phy_power = NULL; in ixgbe_get_invariants_X550_x()
27 link->addr = IXGBE_CS4227; in ixgbe_get_invariants_X550_x()
34 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_get_invariants_X550_x_fw() local
39 phy->ops.set_phy_power = NULL; in ixgbe_get_invariants_X550_x_fw()
[all …]
/kernel/linux/linux-5.10/drivers/phy/
Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
11 * The first PLL clock macro is used for internal reference clock. The second
12 * PLL clock macro is used to generate the clock for the PHY. This driver
13 * configures the first PLL CMU, the second PLL CMU, and programs the PHY to
15 * required if internal clock is enabled.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
[all …]
/kernel/linux/linux-6.6/drivers/phy/
Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
11 * The first PLL clock macro is used for internal reference clock. The second
12 * PLL clock macro is used to generate the clock for the PHY. This driver
13 * configures the first PLL CMU, the second PLL CMU, and programs the PHY to
15 * required if internal clock is enabled.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
[all …]
/kernel/linux/linux-5.10/drivers/net/phy/
Dbcm7xxx.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Broadcom BCM7xxx internal transceivers support.
5 * Copyright (C) 2014-2017 Broadcom
9 #include <linux/phy.h>
11 #include "bcm-phy-lib.h"
17 /* Broadcom BCM7xxx internal PHY registers */
59 /* AFE_RXCONFIG_2, set rCal offset for HT=0 code and LT=-2 code */ in bcm7xxx_28nm_d0_afe_config_init()
74 /* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal in bcm7xxx_28nm_d0_afe_config_init()
79 /* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */ in bcm7xxx_28nm_d0_afe_config_init()
102 /* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal in bcm7xxx_28nm_e0_plus_afe_config_init()
[all …]
Dbroadcom.c1 // SPDX-License-Identifier: GPL-2.0+
3 * drivers/net/phy/broadcom.c
13 #include "bcm-phy-lib.h"
16 #include <linux/phy.h>
21 ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
24 ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))
26 MODULE_DESCRIPTION("Broadcom PHY driver");
34 /* handling PHY's internal RX clock delay */ in bcm54xx_config_clock_delay()
37 if (phydev->interface == PHY_INTERFACE_MODE_RGMII || in bcm54xx_config_clock_delay()
38 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { in bcm54xx_config_clock_delay()
[all …]
Dmicrel.c1 // SPDX-License-Identifier: GPL-2.0+
3 * drivers/net/phy/micrel.c
9 * Copyright (c) 2010-2013 Micrel, Inc.
25 #include <linux/phy.h>
52 /* PHY Control 1 */
55 /* PHY Control 2 / PHY Control (if no PHY Control 1) */
58 /* bitmap of PHY register to set interrupt mode */
160 const struct kszphy_type *type = phydev->drv->driver_data; in kszphy_config_intr()
164 if (type && type->interrupt_level_mask) in kszphy_config_intr()
165 mask = type->interrupt_level_mask; in kszphy_config_intr()
[all …]
Ddp83867.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Driver for the Texas Instruments DP83867 PHY
12 #include <linux/phy.h>
18 #include <dt-bindings/net/ti-dp83867.h>
99 /* PHY CTRL bits */
124 /* PHY STS bits */
185 struct net_device *ndev = phydev->attached_dev; in dp83867_set_wol()
192 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST | in dp83867_set_wol()
197 if (wol->wolopts & WAKE_MAGIC) { in dp83867_set_wol()
198 mac = (u8 *)ndev->dev_addr; in dp83867_set_wol()
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Ds3c6410-smdk6410.dts1 // SPDX-License-Identifier: GPL-2.0
11 /dts-v1/;
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
31 fin_pll: oscillator-0 {
32 compatible = "fixed-clock";
33 clock-frequency = <12000000>;
34 clock-output-names = "fin_pll";
35 #clock-cells = <0>;
38 xusbxti: oscillator-1 {
[all …]
Dexynos5410-smdk5410.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/irq.h>
22 stdout-path = "serial2:115200n8";
26 compatible = "fixed-clock";
27 clock-frequency = <24000000>;
28 clock-output-names = "fin_pll";
29 #clock-cells = <0>;
32 pmic_ap_clk: pmic-ap-clk {
34 compatible = "fixed-clock";
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/samsung/
Ds3c6410-smdk6410.dts1 // SPDX-License-Identifier: GPL-2.0
11 /dts-v1/;
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
31 fin_pll: oscillator-0 {
32 compatible = "fixed-clock";
33 clock-frequency = <12000000>;
34 clock-output-names = "fin_pll";
35 #clock-cells = <0>;
38 xusbxti: oscillator-1 {
[all …]
/kernel/linux/linux-6.6/Documentation/networking/device_drivers/ethernet/stmicro/
Dstmmac.rst1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
33 (and older) and DesignWare(R) Cores Ethernet Quality-of-Service version 4.0
35 DesignWare(R) Cores XGMAC - 10G Ethernet MAC and DesignWare(R) Cores
[all …]
/kernel/linux/linux-5.10/Documentation/networking/device_drivers/ethernet/stmicro/
Dstmmac.rst1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
33 (and older) and DesignWare(R) Cores Ethernet Quality-of-Service version 4.0
35 DesignWare(R) Cores XGMAC - 10G Ethernet MAC and DesignWare(R) Cores
[all …]
/kernel/linux/linux-5.10/drivers/mmc/host/
Dsdhci-xenon.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Date: 2016-8-24
21 #include "sdhci-pltfm.h"
22 #include "sdhci-xenon.h"
41 dev_err(mmc_dev(host->mmc), "Internal clock never stabilised.\n"); in xenon_enable_internal_clk()
42 return -ETIMEDOUT; in xenon_enable_internal_clk()
50 /* Set SDCLK-off-while-idle */
91 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; in xenon_enable_sdhc()
93 * Force to clear BUS_TEST to in xenon_enable_sdhc()
96 host->mmc->caps &= ~MMC_CAP_BUS_WIDTH_TEST; in xenon_enable_sdhc()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Dexynos-srom.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/exynos-srom.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
19 - const: samsung,exynos4210-srom
24 "#address-cells":
27 "#size-cells":
33 <bank-number> 0 <parent address of bank> <size>
37 "^.*@[0-3],[a-f0-9]+$":
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/marvell/
Dsky2.h1 /* SPDX-License-Identifier: GPL-2.0 */
30 /* Yukon-2 */
32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
44 PCI_FORCE_PEX_L1 = 1<<5, /* Force to PEX L1 */
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/marvell/
Dsky2.h1 /* SPDX-License-Identifier: GPL-2.0 */
30 /* Yukon-2 */
32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
44 PCI_FORCE_PEX_L1 = 1<<5, /* Force to PEX L1 */
[all …]
/kernel/linux/linux-6.6/drivers/mmc/host/
Dsdhci-xenon.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Date: 2016-8-24
22 #include "sdhci-pltfm.h"
23 #include "sdhci-xenon.h"
42 dev_err(mmc_dev(host->mmc), "Internal clock never stabilised.\n"); in xenon_enable_internal_clk()
43 return -ETIMEDOUT; in xenon_enable_internal_clk()
51 /* Set SDCLK-off-while-idle */
92 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; in xenon_enable_sdhc()
94 * Force to clear BUS_TEST to in xenon_enable_sdhc()
97 host->mmc->caps &= ~MMC_CAP_BUS_WIDTH_TEST; in xenon_enable_sdhc()
[all …]

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