Searched +full:four +full:- +full:cell (Results 1 – 25 of 147) sorted by relevance
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | ti,c64x+megamod-pic.txt | 2 -------------------
8 Priority 2 and 3 are reserved. Priority 4-15 are used for interrupt
12 --------------------
13 - compatible: Should be "ti,c64x+core-pic";
14 - #interrupt-cells: <1>
17 ------------------------------
18 Single cell specifying the core interrupt priority level (4-15) where
22 -------
23 core_pic: interrupt-controller@0 {
24 interrupt-controller;
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/power/supply/ |
| D | sbs,sbs-manager.txt | 1 Binding for sbs-manager
4 - compatible: "<vendor>,<part-number>", "sbs,sbs-charger" as fallback. The part
7 - reg: integer, i2c address of the device. Should be <0xa>.
9 - gpio-controller: Marks the port as GPIO controller.
10 See "gpio-specifier" in .../devicetree/bindings/gpio/gpio.txt.
11 - #gpio-cells: Should be <2>. The first cell is the pin number, the second cell
13 See "gpio-specifier" in .../devicetree/bindings/gpio/gpio.txt.
15 From OS view the device is basically an i2c-mux used to communicate with up to
16 four smart battery devices at address 0xb. The driver actually implements this
17 behaviour. So standard i2c-mux nodes can be used to register up to four slave
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/ |
| D | cavium-mix.txt | 4 - compatible: "cavium,octeon-5750-mix"
9 - reg: The base addresses of four separate register banks. The first
15 - cell-index: A single cell specifying which portion of the shared
18 - interrupts: Two interrupt specifiers. The first is the MIX
21 - phy-handle: Optional, see ethernet.txt file in the same directory.
25 compatible = "cavium,octeon-5750-mix";
30 cell-index = <1>;
32 local-mac-address = [ 00 0f b7 10 63 54 ];
33 phy-handle = <&phy1>;
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/ |
| D | cavium-mix.txt | 4 - compatible: "cavium,octeon-5750-mix"
9 - reg: The base addresses of four separate register banks. The first
15 - cell-index: A single cell specifying which portion of the shared
18 - interrupts: Two interrupt specifiers. The first is the MIX
21 - phy-handle: Optional, see ethernet.txt file in the same directory.
25 compatible = "cavium,octeon-5750-mix";
30 cell-index = <1>;
32 local-mac-address = [ 00 0f b7 10 63 54 ];
33 phy-handle = <&phy1>;
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| /kernel/linux/linux-6.6/arch/powerpc/include/asm/ |
| D | cell-pmu.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Cell Broadband Engine Performance Monitor
15 /* The Cell PMU has four hardware performance counters, which can be
16 * configured as four 32-bit counters or eight 16-bit counters.
22 #define CBE_PM_16BIT_CTR(ctr) (1 << (24 - ((ctr) & (NR_PHYS_CTRS - 1))))
52 #define CBE_PM_CTR_OVERFLOW_INTR(ctr) (1 << (31 - ((ctr) & 7)))
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| /kernel/linux/linux-5.10/arch/powerpc/include/asm/ |
| D | cell-pmu.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Cell Broadband Engine Performance Monitor
15 /* The Cell PMU has four hardware performance counters, which can be
16 * configured as four 32-bit counters or eight 16-bit counters.
22 #define CBE_PM_16BIT_CTR(ctr) (1 << (24 - ((ctr) & (NR_PHYS_CTRS - 1))))
52 #define CBE_PM_CTR_OVERFLOW_INTR(ctr) (1 << (31 - ((ctr) & 7)))
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/gpio/ |
| D | cavium-octeon-gpio.txt | 4 - compatible: "cavium,octeon-3860-gpio"
8 - reg: The base address of the GPIO unit's register bank.
10 - gpio-controller: This is a GPIO controller.
12 - #gpio-cells: Must be <2>. The first cell is the GPIO pin.
14 - interrupt-controller: The GPIO controller is also an interrupt
18 - #interrupt-cells: Must be <2>. The first cell is the GPIO pin
19 connected to the interrupt source. The second cell is the interrupt
20 triggering protocol and may have one of four values:
21 1 - edge triggered on the rising edge.
22 2 - edge triggered on the falling edge
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/gpio/ |
| D | cavium-octeon-gpio.txt | 4 - compatible: "cavium,octeon-3860-gpio"
8 - reg: The base address of the GPIO unit's register bank.
10 - gpio-controller: This is a GPIO controller.
12 - #gpio-cells: Must be <2>. The first cell is the GPIO pin.
14 - interrupt-controller: The GPIO controller is also an interrupt
18 - #interrupt-cells: Must be <2>. The first cell is the GPIO pin
19 connected to the interrupt source. The second cell is the interrupt
20 triggering protocol and may have one of four values:
21 1 - edge triggered on the rising edge.
22 2 - edge triggered on the falling edge
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/rtc/ |
| D | qcom-pm8xxx-rtc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/qcom-pm8xxx-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Satya Priya <quic_c_skakit@quicinc.com>
15 - enum:
16 - qcom,pm8058-rtc
17 - qcom,pm8921-rtc
18 - qcom,pm8941-rtc
19 - qcom,pmk8350-rtc
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | stericsson,u8500-clks.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/stericsson,u8500-clks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DB8500 (U8500) clocks
10 - Ulf Hansson <ulf.hansson@linaro.org>
11 - Linus Walleij <linus.walleij@linaro.org>
14 DB8500 digital baseband system-on-chip and its siblings such as
16 itself, not off-chip clocks. There are four different on-chip
17 clocks - RTC (32 kHz), CPU clock (SMP TWD), PRCMU (power reset and
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/dma/ |
| D | renesas,rzn1-dmamux.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/renesas,rzn1-dmamux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: dma-router.yaml#
17 const: renesas,rzn1-dmamux
23 '#dma-cells':
26 The first four cells are dedicated to the master DMA controller. The fifth
27 cell gives the DMA mux bit index that must be set starting from 0. The
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/sound/ |
| D | cirrus,madera.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - patches@opensource.cirrus.com
21 include/dt-bindings/sound/madera.h
26 - $ref: dai-common.yaml#
29 '#sound-dai-cells':
31 The first cell indicating the audio interface.
37 of 24 cells, with four cells per input in the order INnAL,
38 INnAR INnBL INnBR. For non-muxed inputs the first two cells
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/ |
| D | cirrus,madera.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - patches@opensource.cirrus.com
21 include/dt-bindings/sound/madera.h
26 '#sound-dai-cells':
28 The first cell indicating the audio interface.
34 of 24 cells, with four cells per input in the order INnAL,
35 INnAR INnBL INnBR. For non-muxed inputs the first two cells
43 $ref: /schemas/types.yaml#/definitions/uint32-array
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mfd/ |
| D | ti,lp87561-q1.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/ti,lp87561-q1.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI LP87561-Q1 single 4-phase output buck converter
10 - Keerthy <j-keerthy@ti.com>
14 const: ti,lp87561-q1
20 gpio-controller: true
22 '#gpio-cells':
24 The first cell is the pin number.
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| D | ti,lp87524-q1.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/ti,lp87524-q1.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI LP87524-Q1 four 1-phase output buck converter
10 - Keerthy <j-keerthy@ti.com>
14 const: ti,lp87524-q1
20 gpio-controller: true
22 '#gpio-cells':
24 The first cell is the pin number.
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/mfd/ |
| D | ti,lp87561-q1.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/ti,lp87561-q1.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI LP87561-Q1 single 4-phase output buck converter
10 - Keerthy <j-keerthy@ti.com>
14 const: ti,lp87561-q1
20 reset-gpios:
24 gpio-controller: true
26 '#gpio-cells':
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| D | ti,lp87524-q1.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/ti,lp87524-q1.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI LP87524-Q1 four 1-phase output buck converter
10 - Keerthy <j-keerthy@ti.com>
14 const: ti,lp87524-q1
20 reset-gpios:
24 gpio-controller: true
26 '#gpio-cells':
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/ |
| D | fsl,imx8qm-lvds-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8qm-lvds-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
14 It converts two groups of four 7/10 bits of CMOS data into two
15 groups of four data lanes of LVDS data streams. A phase-locked
30 - fsl,imx8qm-lvds-phy
31 - mixel,28fdsoi-lvds-1250-8ch-tx-pll
33 "#phy-cells":
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| /kernel/linux/linux-5.10/Documentation/userspace-api/media/v4l/ |
| D | pixfmt-yuv410.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-YVU410:
4 .. _v4l2-pix-fmt-yuv410:
20 components are separated into three sub-images or planes. The Y plane is
24 belongs to 16 pixels, a four-by-four square of the image. Following the
30 have ¼ as many pad bytes after their rows. In other words, four Cx rows
35 Each cell is one byte.
40 .. flat-table::
41 :header-rows: 0
42 :stub-columns: 0
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| D | pixfmt-yvyu.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-YVYU:
17 In this format each four bytes is two pixels. Each four bytes is two
23 Each cell is one byte.
26 .. flat-table::
27 :header-rows: 0
28 :stub-columns: 0
30 * - start + 0:
31 - Y'\ :sub:`00`
32 - Cr\ :sub:`00`
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| D | pixfmt-vyuy.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-VYUY:
17 In this format each four bytes is two pixels. Each four bytes is two
23 Each cell is one byte.
26 .. flat-table::
27 :header-rows: 0
28 :stub-columns: 0
30 * - start + 0:
31 - Cr\ :sub:`00`
32 - Y'\ :sub:`00`
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| D | pixfmt-uyvy.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-UYVY:
17 In this format each four bytes is two pixels. Each four bytes is two
23 Each cell is one byte.
26 .. flat-table::
27 :header-rows: 0
28 :stub-columns: 0
30 * - start + 0:
31 - Cb\ :sub:`00`
32 - Y'\ :sub:`00`
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| D | pixfmt-yuyv.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-YUYV:
17 In this format each four bytes is two pixels. Each four bytes is two
24 Each cell is one byte.
29 .. flat-table::
30 :header-rows: 0
31 :stub-columns: 0
33 * - start + 0:
34 - Y'\ :sub:`00`
35 - Cb\ :sub:`00`
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/soc/fsl/cpm_qe/ |
| D | gpio.txt | 1 Every GPIO controller node must have #gpio-cells property defined,
2 this information will be used to translate gpio-specifiers.
10 - compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b",
11 "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d",
12 "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank"
13 - #gpio-cells : Should be two. The first cell is the pin number and the
14 second cell is used to specify optional parameters (currently unused).
15 - gpio-controller : Marks the port as GPIO controller.
17 - fsl,cpm1-gpio-irq-mask : For banks having interrupt capability (like port C
20 - interrupts : This property provides the list of interrupt for each GPIO having
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/fsl/cpm_qe/ |
| D | gpio.txt | 1 Every GPIO controller node must have #gpio-cells property defined,
2 this information will be used to translate gpio-specifiers.
10 - compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b",
11 "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d",
12 "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank"
13 - #gpio-cells : Should be two. The first cell is the pin number and the
14 second cell is used to specify optional parameters (currently unused).
15 - gpio-controller : Marks the port as GPIO controller.
17 - fsl,cpm1-gpio-irq-mask : For banks having interrupt capability (like port C
20 - interrupts : This property provides the list of interrupt for each GPIO having
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