| /kernel/linux/linux-5.10/drivers/fpga/ |
| D | fpga-mgr.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Manager Core
5 * Copyright (C) 2013-2015 Altera Corporation
12 #include <linux/fpga/fpga-mgr.h>
25 * fpga_image_info_alloc - Allocate a FPGA image info struct
42 info->dev = dev; in fpga_image_info_alloc()
49 * fpga_image_info_free - Free a FPGA image info struct
50 * @info: FPGA image info struct to free
59 dev = info->dev; in fpga_image_info_free()
60 if (info->firmware_name) in fpga_image_info_free()
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| D | dfl-fme-region.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Region Driver for FPGA Management Engine (FME)
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
17 #include <linux/fpga/fpga-mgr.h>
18 #include <linux/fpga/fpga-region.h>
20 #include "dfl-fme-pr.h"
24 struct dfl_fme_region_pdata *pdata = region->priv; in fme_region_get_bridges()
25 struct device *dev = &pdata->br->dev; in fme_region_get_bridges()
27 return fpga_bridge_get_to_list(dev, region->info, ®ion->bridge_list); in fme_region_get_bridges()
32 struct dfl_fme_region_pdata *pdata = dev_get_platdata(&pdev->dev); in fme_region_probe()
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| D | ts73xx-fpga.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Technologic Systems TS-73xx SBC FPGA loader
7 * FPGA Manager Driver for the on-board Altera Cyclone II FPGA found on
8 * TS-7300, heavily based on load_fpga.c in their vendor tree.
17 #include <linux/fpga/fpga-mgr.h>
35 static enum fpga_mgr_states ts73xx_fpga_state(struct fpga_manager *mgr) in ts73xx_fpga_state() argument
40 static int ts73xx_fpga_write_init(struct fpga_manager *mgr, in ts73xx_fpga_write_init() argument
44 struct ts73xx_fpga_priv *priv = mgr->priv; in ts73xx_fpga_write_init()
46 /* Reset the FPGA */ in ts73xx_fpga_write_init()
47 writeb(0, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_init()
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| D | dfl-fme-pr.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for FPGA Management Engine (FME) Partial Reconfiguration
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
23 #include <linux/fpga/fpga-mgr.h>
24 #include <linux/fpga/fpga-bridge.h>
25 #include <linux/fpga/fpga-region.h>
26 #include <linux/fpga-dfl.h>
29 #include "dfl-fme.h"
30 #include "dfl-fme-pr.h"
37 list_for_each_entry(fme_region, &fme->region_list, node) in dfl_fme_region_find_by_port_id()
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| D | of-fpga-region.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Region - Device Tree support for FPGA programming under Linux
5 * Copyright (C) 2013-2016 Altera Corporation
8 #include <linux/fpga/fpga-bridge.h>
9 #include <linux/fpga/fpga-mgr.h>
10 #include <linux/fpga/fpga-region.h>
20 { .compatible = "fpga-region", },
26 * of_fpga_region_find - find FPGA region
27 * @np: device node of FPGA Region
29 * Caller will need to put_device(®ion->dev) when done.
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| D | stratix10-soc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Manager Driver for Intel Stratix10 SoC
8 #include <linux/fpga/fpga-mgr.h>
9 #include <linux/firmware/intel/stratix10-svc-client.h>
15 * FPGA programming requires a higher level of privilege (EL3), per the SoC
49 struct stratix10_svc_chan *chan = priv->chan; in s10_svc_send_msg()
50 struct device *dev = priv->client.dev; in s10_svc_send_msg()
71 static bool s10_free_buffers(struct fpga_manager *mgr) in s10_free_buffers() argument
73 struct s10_priv *priv = mgr->priv; in s10_free_buffers()
78 if (!priv->svc_bufs[i].buf) { in s10_free_buffers()
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| D | fpga-region.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Region - Support for FPGA programming under Linux
5 * Copyright (C) 2013-2016 Altera Corporation
8 #include <linux/fpga/fpga-bridge.h>
9 #include <linux/fpga/fpga-mgr.h>
10 #include <linux/fpga/fpga-region.h>
36 * fpga_region_get - get an exclusive reference to a fpga region
37 * @region: FPGA Region struct
42 * Return -EBUSY if someone already has a reference to the region.
43 * Return -ENODEV if @np is not a FPGA Region.
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| D | zynqmp-fpga.c | 1 // SPDX-License-Identifier: GPL-2.0+
6 #include <linux/dma-mapping.h>
7 #include <linux/fpga/fpga-mgr.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
19 * struct zynqmp_fpga_priv - Private data structure
28 static int zynqmp_fpga_ops_write_init(struct fpga_manager *mgr, in zynqmp_fpga_ops_write_init() argument
34 priv = mgr->priv; in zynqmp_fpga_ops_write_init()
35 priv->flags = info->flags; in zynqmp_fpga_ops_write_init()
40 static int zynqmp_fpga_ops_write(struct fpga_manager *mgr, in zynqmp_fpga_ops_write() argument
49 priv = mgr->priv; in zynqmp_fpga_ops_write()
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| D | ice40-spi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * FPGA Manager Driver for Lattice iCE40.
7 * This driver adds support to the FPGA manager for configuring the SRAM of
11 #include <linux/fpga/fpga-mgr.h>
32 static enum fpga_mgr_states ice40_fpga_ops_state(struct fpga_manager *mgr) in ice40_fpga_ops_state() argument
34 struct ice40_fpga_priv *priv = mgr->priv; in ice40_fpga_ops_state()
36 return gpiod_get_value(priv->cdone) ? FPGA_MGR_STATE_OPERATING : in ice40_fpga_ops_state()
40 static int ice40_fpga_ops_write_init(struct fpga_manager *mgr, in ice40_fpga_ops_write_init() argument
44 struct ice40_fpga_priv *priv = mgr->priv; in ice40_fpga_ops_write_init()
45 struct spi_device *dev = priv->dev; in ice40_fpga_ops_write_init()
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| D | xilinx-spi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 * Manage Xilinx FPGA firmware that is loaded over SPI using
15 #include <linux/fpga/fpga-mgr.h>
30 static int get_done_gpio(struct fpga_manager *mgr) in get_done_gpio() argument
32 struct xilinx_spi_conf *conf = mgr->priv; in get_done_gpio()
35 ret = gpiod_get_value(conf->done); in get_done_gpio()
38 dev_err(&mgr->dev, "Error reading DONE (%d)\n", ret); in get_done_gpio()
43 static enum fpga_mgr_states xilinx_spi_state(struct fpga_manager *mgr) in xilinx_spi_state() argument
45 if (!get_done_gpio(mgr)) in xilinx_spi_state()
52 * wait_for_init_b - wait for the INIT_B pin to have a given state, or wait
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| /kernel/linux/linux-6.6/drivers/fpga/ |
| D | fpga-mgr.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Manager Core
5 * Copyright (C) 2013-2015 Altera Corporation
12 #include <linux/fpga/fpga-mgr.h>
25 struct fpga_manager *mgr; member
28 static inline void fpga_mgr_fpga_remove(struct fpga_manager *mgr) in fpga_mgr_fpga_remove() argument
30 if (mgr->mops->fpga_remove) in fpga_mgr_fpga_remove()
31 mgr->mops->fpga_remove(mgr); in fpga_mgr_fpga_remove()
34 static inline enum fpga_mgr_states fpga_mgr_state(struct fpga_manager *mgr) in fpga_mgr_state() argument
36 if (mgr->mops->state) in fpga_mgr_state()
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| D | dfl-fme-region.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Region Driver for FPGA Management Engine (FME)
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
17 #include <linux/fpga/fpga-mgr.h>
18 #include <linux/fpga/fpga-region.h>
20 #include "dfl-fme-pr.h"
24 struct dfl_fme_region_pdata *pdata = region->priv; in fme_region_get_bridges()
25 struct device *dev = &pdata->br->dev; in fme_region_get_bridges()
27 return fpga_bridge_get_to_list(dev, region->info, ®ion->bridge_list); in fme_region_get_bridges()
32 struct dfl_fme_region_pdata *pdata = dev_get_platdata(&pdev->dev); in fme_region_probe()
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| D | dfl-fme-pr.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for FPGA Management Engine (FME) Partial Reconfiguration
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
23 #include <linux/fpga/fpga-mgr.h>
24 #include <linux/fpga/fpga-bridge.h>
25 #include <linux/fpga/fpga-region.h>
26 #include <linux/fpga-dfl.h>
29 #include "dfl-fme.h"
30 #include "dfl-fme-pr.h"
37 list_for_each_entry(fme_region, &fme->region_list, node) in dfl_fme_region_find_by_port_id()
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| D | of-fpga-region.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Region - Device Tree support for FPGA programming under Linux
5 * Copyright (C) 2013-2016 Altera Corporation
8 #include <linux/fpga/fpga-bridge.h>
9 #include <linux/fpga/fpga-mgr.h>
10 #include <linux/fpga/fpga-region.h>
22 { .compatible = "fpga-region", },
28 * of_fpga_region_find - find FPGA region
29 * @np: device node of FPGA Region
31 * Caller will need to put_device(®ion->dev) when done.
[all …]
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| D | ts73xx-fpga.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Technologic Systems TS-73xx SBC FPGA loader
7 * FPGA Manager Driver for the on-board Altera Cyclone II FPGA found on
8 * TS-7300, heavily based on load_fpga.c in their vendor tree.
17 #include <linux/fpga/fpga-mgr.h>
35 static int ts73xx_fpga_write_init(struct fpga_manager *mgr, in ts73xx_fpga_write_init() argument
39 struct ts73xx_fpga_priv *priv = mgr->priv; in ts73xx_fpga_write_init()
41 /* Reset the FPGA */ in ts73xx_fpga_write_init()
42 writeb(0, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_init()
44 writeb(TS73XX_FPGA_RESET, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_init()
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| D | fpga-region.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Region - Support for FPGA programming under Linux
5 * Copyright (C) 2013-2016 Altera Corporation
8 #include <linux/fpga/fpga-bridge.h>
9 #include <linux/fpga/fpga-mgr.h>
10 #include <linux/fpga/fpga-region.h>
36 * fpga_region_get - get an exclusive reference to an fpga region
37 * @region: FPGA Region struct
43 * * -EBUSY if someone already has a reference to the region.
44 * * -ENODEV if can't take parent driver module refcount.
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| D | stratix10-soc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Manager Driver for Intel Stratix10 SoC
8 #include <linux/fpga/fpga-mgr.h>
9 #include <linux/firmware/intel/stratix10-svc-client.h>
16 * FPGA programming requires a higher level of privilege (EL3), per the SoC
50 struct stratix10_svc_chan *chan = priv->chan; in s10_svc_send_msg()
51 struct device *dev = priv->client.dev; in s10_svc_send_msg()
72 static bool s10_free_buffers(struct fpga_manager *mgr) in s10_free_buffers() argument
74 struct s10_priv *priv = mgr->priv; in s10_free_buffers()
79 if (!priv->svc_bufs[i].buf) { in s10_free_buffers()
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| D | ice40-spi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * FPGA Manager Driver for Lattice iCE40.
7 * This driver adds support to the FPGA manager for configuring the SRAM of
11 #include <linux/fpga/fpga-mgr.h>
32 static enum fpga_mgr_states ice40_fpga_ops_state(struct fpga_manager *mgr) in ice40_fpga_ops_state() argument
34 struct ice40_fpga_priv *priv = mgr->priv; in ice40_fpga_ops_state()
36 return gpiod_get_value(priv->cdone) ? FPGA_MGR_STATE_OPERATING : in ice40_fpga_ops_state()
40 static int ice40_fpga_ops_write_init(struct fpga_manager *mgr, in ice40_fpga_ops_write_init() argument
44 struct ice40_fpga_priv *priv = mgr->priv; in ice40_fpga_ops_write_init()
45 struct spi_device *dev = priv->dev; in ice40_fpga_ops_write_init()
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| /kernel/linux/linux-6.6/Documentation/driver-api/fpga/ |
| D | fpga-mgr.rst | 1 FPGA Manager
5 --------
7 The FPGA manager core exports a set of functions for programming an FPGA with
10 The FPGA image data itself is very manufacturer specific, but for our purposes
11 it's just binary data. The FPGA manager core won't parse it.
13 The FPGA image to be programmed can be in a scatter gather list, a single
20 FPGA image as well as image-specific particulars such as whether the image was
23 How to support a new FPGA device
24 --------------------------------
26 To add another FPGA manager, write a driver that implements a set of ops. The
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| D | fpga-programming.rst | 1 In-kernel API for FPGA Programming
5 --------
7 The in-kernel API for FPGA programming is a combination of APIs from
8 FPGA manager, bridge, and regions. The actual function used to
9 trigger FPGA programming is fpga_region_program_fpga().
12 the FPGA manager and bridges. It will:
15 * lock the mutex of the region's FPGA manager
16 * build a list of FPGA bridges if a method has been specified to do so
18 * program the FPGA using info passed in :c:expr:`fpga_region->info`.
19 * re-enable the bridges
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| /kernel/linux/linux-5.10/Documentation/driver-api/fpga/ |
| D | fpga-mgr.rst | 1 FPGA Manager
5 --------
7 The FPGA manager core exports a set of functions for programming an FPGA with
10 The FPGA image data itself is very manufacturer specific, but for our purposes
11 it's just binary data. The FPGA manager core won't parse it.
13 The FPGA image to be programmed can be in a scatter gather list, a single
20 FPGA image as well as image-specific particulars such as whether the image was
23 How to support a new FPGA device
24 --------------------------------
26 To add another FPGA manager, write a driver that implements a set of ops. The
[all …]
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| /kernel/linux/linux-5.10/include/linux/fpga/ |
| D | fpga-mgr.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * FPGA Framework
5 * Copyright (C) 2013-2016 Altera Corporation
18 * enum fpga_mgr_states - fpga framework states
20 * @FPGA_MGR_STATE_POWER_OFF: FPGA power is off
21 * @FPGA_MGR_STATE_POWER_UP: FPGA reports power is up
22 * @FPGA_MGR_STATE_RESET: FPGA in reset state
25 * @FPGA_MGR_STATE_WRITE_INIT: preparing FPGA for programming
27 * @FPGA_MGR_STATE_WRITE: writing image to FPGA
28 * @FPGA_MGR_STATE_WRITE_ERR: Error while writing FPGA
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| D | fpga-region.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <linux/fpga/fpga-mgr.h>
8 #include <linux/fpga/fpga-bridge.h>
11 * struct fpga_region - FPGA Region structure
12 * @dev: FPGA Region device
14 * @bridge_list: list of FPGA bridges specified in region
15 * @mgr: FPGA manager
16 * @info: FPGA image info
17 * @compat_id: FPGA region id for compatibility check.
25 struct fpga_manager *mgr; member
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| /kernel/linux/linux-6.6/include/linux/fpga/ |
| D | fpga-mgr.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * FPGA Framework
5 * Copyright (C) 2013-2016 Altera Corporation
18 * enum fpga_mgr_states - fpga framework states
20 * @FPGA_MGR_STATE_POWER_OFF: FPGA power is off
21 * @FPGA_MGR_STATE_POWER_UP: FPGA reports power is up
22 * @FPGA_MGR_STATE_RESET: FPGA in reset state
25 * @FPGA_MGR_STATE_PARSE_HEADER: parse FPGA image header
27 * @FPGA_MGR_STATE_WRITE_INIT: preparing FPGA for programming
29 * @FPGA_MGR_STATE_WRITE: writing image to FPGA
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| D | fpga-region.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <linux/fpga/fpga-mgr.h>
8 #include <linux/fpga/fpga-bridge.h>
13 * struct fpga_region_info - collection of parameters an FPGA Region
14 * @mgr: fpga region manager
15 * @compat_id: FPGA region id for compatibility check.
16 * @priv: fpga region private data
25 struct fpga_manager *mgr; member
32 * struct fpga_region - FPGA Region structure
33 * @dev: FPGA Region device
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