| /kernel/linux/linux-6.6/Documentation/driver-api/fpga/ |
| D | fpga-region.rst | 1 FPGA Region
5 --------
7 This document is meant to be a brief overview of the FPGA region API usage. A
11 For the purposes of this API document, let's just say that a region associates
12 an FPGA Manager and a bridge (or bridges) with a reprogrammable region of an
13 FPGA or the whole FPGA. The API provides a way to register a region and to
14 program a region.
16 Currently the only layer above fpga-region.c in the kernel is the Device Tree
17 support (of-fpga-region.c) described in [#f1]_. The DT support layer uses regions
18 to program the FPGA and then DT to handle enumeration. The common region code
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| D | intro.rst | 4 The FPGA subsystem supports reprogramming FPGAs dynamically under
5 Linux. Some of the core intentions of the FPGA subsystems are:
7 * The FPGA subsystem is vendor agnostic.
9 * The FPGA subsystem separates upper layers (userspace interfaces and
11 FPGA.
16 other users. Write the linux-fpga mailing list and maintainers and
23 FPGA Manager
24 ------------
26 If you are adding a new FPGA or a new method of programming an FPGA,
27 this is the subsystem for you. Low level FPGA manager drivers contain
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| D | fpga-programming.rst | 1 In-kernel API for FPGA Programming
5 --------
7 The in-kernel API for FPGA programming is a combination of APIs from
8 FPGA manager, bridge, and regions. The actual function used to
9 trigger FPGA programming is fpga_region_program_fpga().
12 the FPGA manager and bridges. It will:
14 * lock the region's mutex
15 * lock the mutex of the region's FPGA manager
16 * build a list of FPGA bridges if a method has been specified to do so
18 * program the FPGA using info passed in :c:expr:`fpga_region->info`.
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/fpga/ |
| D | fpga-region.txt | 1 FPGA Region Device Tree Binding
6 - Introduction
7 - Terminology
8 - Sequence
9 - FPGA Region
10 - Supported Use Models
11 - Device Tree Examples
12 - Constraints
18 FPGA Regions represent FPGA's and partial reconfiguration regions of FPGA's in
19 the Device Tree. FPGA Regions provide a way to program FPGAs under device tree
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/fpga/ |
| D | fpga-region.txt | 1 FPGA Region Device Tree Binding
6 - Introduction
7 - Terminology
8 - Sequence
9 - FPGA Region
10 - Supported Use Models
11 - Device Tree Examples
12 - Constraints
18 FPGA Regions represent FPGA's and partial reconfiguration regions of FPGA's in
19 the Device Tree. FPGA Regions provide a way to program FPGAs under device tree
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| /kernel/linux/linux-5.10/Documentation/driver-api/fpga/ |
| D | fpga-region.rst | 1 FPGA Region
5 --------
7 This document is meant to be a brief overview of the FPGA region API usage. A
11 For the purposes of this API document, let's just say that a region associates
12 an FPGA Manager and a bridge (or bridges) with a reprogrammable region of an
13 FPGA or the whole FPGA. The API provides a way to register a region and to
14 program a region.
16 Currently the only layer above fpga-region.c in the kernel is the Device Tree
17 support (of-fpga-region.c) described in [#f1]_. The DT support layer uses regions
18 to program the FPGA and then DT to handle enumeration. The common region code
[all …]
|
| D | intro.rst | 4 The FPGA subsystem supports reprogramming FPGAs dynamically under
5 Linux. Some of the core intentions of the FPGA subsystems are:
7 * The FPGA subsystem is vendor agnostic.
9 * The FPGA subsystem separates upper layers (userspace interfaces and
11 FPGA.
16 other users. Write the linux-fpga mailing list and maintainers and
23 FPGA Manager
24 ------------
26 If you are adding a new FPGA or a new method of programming an FPGA,
27 this is the subsystem for you. Low level FPGA manager drivers contain
[all …]
|
| D | fpga-programming.rst | 1 In-kernel API for FPGA Programming
5 --------
7 The in-kernel API for FPGA programming is a combination of APIs from
8 FPGA manager, bridge, and regions. The actual function used to
9 trigger FPGA programming is fpga_region_program_fpga().
12 the FPGA manager and bridges. It will:
14 * lock the region's mutex
15 * lock the mutex of the region's FPGA manager
16 * build a list of FPGA bridges if a method has been specified to do so
18 * program the FPGA using info passed in :c:expr:`fpga_region->info`.
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| /kernel/linux/linux-6.6/drivers/fpga/ |
| D | of-fpga-region.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Region - Device Tree support for FPGA programming under Linux
5 * Copyright (C) 2013-2016 Altera Corporation
8 #include <linux/fpga/fpga-bridge.h>
9 #include <linux/fpga/fpga-mgr.h>
10 #include <linux/fpga/fpga-region.h>
22 { .compatible = "fpga-region", },
28 * of_fpga_region_find - find FPGA region
29 * @np: device node of FPGA Region
31 * Caller will need to put_device(®ion->dev) when done.
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| D | fpga-region.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Region - Support for FPGA programming under Linux
5 * Copyright (C) 2013-2016 Altera Corporation
8 #include <linux/fpga/fpga-bridge.h>
9 #include <linux/fpga/fpga-mgr.h>
10 #include <linux/fpga/fpga-region.h>
36 * fpga_region_get - get an exclusive reference to an fpga region
37 * @region: FPGA Region struct
39 * Caller should call fpga_region_put() when done with region.
43 * * -EBUSY if someone already has a reference to the region.
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| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # FPGA framework configuration
6 menuconfig FPGA config
7 tristate "FPGA Configuration Framework"
10 kernel. The FPGA framework adds an FPGA manager class and FPGA
13 if FPGA
16 tristate "Altera SOCFPGA FPGA Manager"
19 FPGA manager driver support for Altera SOCFPGA.
26 FPGA manager driver support for Altera Arria10 SoCFPGA.
41 tristate "Altera FPGA Passive Serial over SPI"
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| D | dfl-fme-region.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Region Driver for FPGA Management Engine (FME)
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
17 #include <linux/fpga/fpga-mgr.h>
18 #include <linux/fpga/fpga-region.h>
20 #include "dfl-fme-pr.h"
22 static int fme_region_get_bridges(struct fpga_region *region) in fme_region_get_bridges() argument
24 struct dfl_fme_region_pdata *pdata = region->priv; in fme_region_get_bridges()
25 struct device *dev = &pdata->br->dev; in fme_region_get_bridges()
27 return fpga_bridge_get_to_list(dev, region->info, ®ion->bridge_list); in fme_region_get_bridges()
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| D | dfl-fme-pr.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for FPGA Management Engine (FME) Partial Reconfiguration
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
23 #include <linux/fpga/fpga-mgr.h>
24 #include <linux/fpga/fpga-bridge.h>
25 #include <linux/fpga/fpga-region.h>
26 #include <linux/fpga-dfl.h>
29 #include "dfl-fme.h"
30 #include "dfl-fme-pr.h"
37 list_for_each_entry(fme_region, &fme->region_list, node) in dfl_fme_region_find_by_port_id()
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| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for the fpga framework and fpga manager drivers.
6 # Core FPGA Manager Framework
7 obj-$(CONFIG_FPGA) += fpga-mgr.o
9 # FPGA Manager Drivers
10 obj-$(CONFIG_FPGA_MGR_ALTERA_CVP) += altera-cvp.o
11 obj-$(CONFIG_FPGA_MGR_ALTERA_PS_SPI) += altera-ps-spi.o
12 obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o
13 obj-$(CONFIG_FPGA_MGR_MACHXO2_SPI) += machxo2-spi.o
14 obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o
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| D | dfl-fme-pr.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Header file for FPGA Management Engine (FME) Partial Reconfiguration Driver
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
24 * struct dfl_fme_region - FME fpga region data structure
26 * @region: platform device of the FPGA region.
28 * @port_id: indicate which port this region connected to.
31 struct platform_device *region; member
37 * struct dfl_fme_region_pdata - platform data for FME region platform device.
39 * @mgr: platform device of the FPGA manager.
40 * @br: platform device of the FPGA bridge.
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| /kernel/linux/linux-5.10/drivers/fpga/ |
| D | of-fpga-region.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Region - Device Tree support for FPGA programming under Linux
5 * Copyright (C) 2013-2016 Altera Corporation
8 #include <linux/fpga/fpga-bridge.h>
9 #include <linux/fpga/fpga-mgr.h>
10 #include <linux/fpga/fpga-region.h>
20 { .compatible = "fpga-region", },
26 * of_fpga_region_find - find FPGA region
27 * @np: device node of FPGA Region
29 * Caller will need to put_device(®ion->dev) when done.
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| D | fpga-region.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Region - Support for FPGA programming under Linux
5 * Copyright (C) 2013-2016 Altera Corporation
8 #include <linux/fpga/fpga-bridge.h>
9 #include <linux/fpga/fpga-mgr.h>
10 #include <linux/fpga/fpga-region.h>
36 * fpga_region_get - get an exclusive reference to a fpga region
37 * @region: FPGA Region struct
39 * Caller should call fpga_region_put() when done with region.
42 * Return -EBUSY if someone already has a reference to the region.
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| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # FPGA framework configuration
6 menuconfig FPGA config
7 tristate "FPGA Configuration Framework"
10 kernel. The FPGA framework adds a FPGA manager class and FPGA
13 if FPGA
16 tristate "Altera SOCFPGA FPGA Manager"
19 FPGA manager driver support for Altera SOCFPGA.
26 FPGA manager driver support for Altera Arria10 SoCFPGA.
41 tristate "Altera FPGA Passive Serial over SPI"
[all …]
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| D | dfl-fme-region.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Region Driver for FPGA Management Engine (FME)
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
17 #include <linux/fpga/fpga-mgr.h>
18 #include <linux/fpga/fpga-region.h>
20 #include "dfl-fme-pr.h"
22 static int fme_region_get_bridges(struct fpga_region *region) in fme_region_get_bridges() argument
24 struct dfl_fme_region_pdata *pdata = region->priv; in fme_region_get_bridges()
25 struct device *dev = &pdata->br->dev; in fme_region_get_bridges()
27 return fpga_bridge_get_to_list(dev, region->info, ®ion->bridge_list); in fme_region_get_bridges()
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| D | dfl-fme-pr.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for FPGA Management Engine (FME) Partial Reconfiguration
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
23 #include <linux/fpga/fpga-mgr.h>
24 #include <linux/fpga/fpga-bridge.h>
25 #include <linux/fpga/fpga-region.h>
26 #include <linux/fpga-dfl.h>
29 #include "dfl-fme.h"
30 #include "dfl-fme-pr.h"
37 list_for_each_entry(fme_region, &fme->region_list, node) in dfl_fme_region_find_by_port_id()
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| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for the fpga framework and fpga manager drivers.
6 # Core FPGA Manager Framework
7 obj-$(CONFIG_FPGA) += fpga-mgr.o
9 # FPGA Manager Drivers
10 obj-$(CONFIG_FPGA_MGR_ALTERA_CVP) += altera-cvp.o
11 obj-$(CONFIG_FPGA_MGR_ALTERA_PS_SPI) += altera-ps-spi.o
12 obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o
13 obj-$(CONFIG_FPGA_MGR_MACHXO2_SPI) += machxo2-spi.o
14 obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o
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| /kernel/linux/linux-6.6/include/linux/fpga/ |
| D | fpga-region.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <linux/fpga/fpga-mgr.h>
8 #include <linux/fpga/fpga-bridge.h>
13 * struct fpga_region_info - collection of parameters an FPGA Region
14 * @mgr: fpga region manager
15 * @compat_id: FPGA region id for compatibility check.
16 * @priv: fpga region private data
28 int (*get_bridges)(struct fpga_region *region);
32 * struct fpga_region - FPGA Region structure
33 * @dev: FPGA Region device
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| /kernel/linux/linux-5.10/include/linux/fpga/ |
| D | fpga-region.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <linux/fpga/fpga-mgr.h>
8 #include <linux/fpga/fpga-bridge.h>
11 * struct fpga_region - FPGA Region structure
12 * @dev: FPGA Region device
13 * @mutex: enforces exclusive reference to region
14 * @bridge_list: list of FPGA bridges specified in region
15 * @mgr: FPGA manager
16 * @info: FPGA image info
17 * @compat_id: FPGA region id for compatibility check.
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| /kernel/linux/linux-6.6/drivers/fpga/tests/ |
| D | fpga-region-test.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * KUnit test for the FPGA Region
11 #include <linux/fpga/fpga-bridge.h>
12 #include <linux/fpga/fpga-mgr.h>
13 #include <linux/fpga/fpga-region.h>
32 struct fpga_region *region; member
40 struct mgr_stats *stats = mgr->priv; in op_write()
42 stats->write_count++; in op_write()
48 * Fake FPGA manager that implements only the write op to count the number
51 * of the Region.
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| /kernel/linux/linux-5.10/Documentation/fpga/ |
| D | dfl.rst | 2 FPGA Device Feature List (DFL) Framework Overview
7 - Enno Luebbers <enno.luebbers@intel.com>
8 - Xiao Guangrong <guangrong.xiao@linux.intel.com>
9 - Wu Hao <hao.wu@intel.com>
11 The Device Feature List (DFL) FPGA framework (and drivers according to
14 configure, enumerate, open and access FPGA accelerators on platforms which
16 enables system level management functions such as FPGA reconfiguration.
23 walk through these predefined data structures to enumerate FPGA features:
24 FPGA Interface Unit (FIU), Accelerated Function Unit (AFU) and Private Features,
28 +----------+ +-->+----------+ +-->+----------+ +-->+----------+
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