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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dbcm283x-rpi-usb-otg.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 g-rx-fifo-size = <256>;
5 g-np-tx-fifo-size = <32>;
8 * fifo sizes shouldn't exceed 3776 bytes.
10 g-tx-fifo-size = <256 256 512 512 512 768 768>;
Dbcm283x-rpi-usb-peripheral.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 g-rx-fifo-size = <256>;
5 g-np-tx-fifo-size = <32>;
6 g-tx-fifo-size = <256 256 512 512 512 768 768>;
Drk3xxx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/soc/rockchip,boot-mode.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 interrupt-parent = <&gic>;
36 compatible = "simple-bus";
37 #address-cells = <1>;
38 #size-cells = <1>;
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/broadcom/
Dbcm283x-rpi-usb-otg.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 g-rx-fifo-size = <256>;
5 g-np-tx-fifo-size = <32>;
8 * fifo sizes shouldn't exceed 3776 bytes.
10 g-tx-fifo-size = <256 256 512 512 512 768 768>;
Dbcm283x-rpi-usb-peripheral.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 g-rx-fifo-size = <256>;
5 g-np-tx-fifo-size = <32>;
6 g-tx-fifo-size = <256 256 512 512 512 768 768>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/
Ddwc2.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
15 - const: brcm,bcm2835-usb
16 - const: hisilicon,hi6220-usb
17 - items:
18 - const: rockchip,rk3066-usb
19 - const: snps,dwc2
20 - items:
[all …]
Damlogic,meson-g12a-usb-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/usb/amlogic,meson-g12a-usb-ctrl.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Neil Armstrong <narmstrong@baylibre.com>
15 in host-only mode, and a DWC2 IP Core configured for USB2 peripheral mode
20 One of the USB2 PHYs can be re-routed in peripheral mode to a DWC2 USB IP.
26 host-only mode.
33 - amlogic,meson-gxl-usb-ctrl
34 - amlogic,meson-gxm-usb-ctrl
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/usb/
Ddwc2.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
13 - $ref: usb-drd.yaml#
14 - $ref: usb-hcd.yaml#
19 - const: brcm,bcm2835-usb
20 - const: hisilicon,hi6220-usb
21 - const: ingenic,jz4775-otg
22 - const: ingenic,jz4780-otg
[all …]
Damlogic,meson-g12a-usb-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/amlogic,meson-g12a-usb-ctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
15 in host-only mode, and a DWC2 IP Core configured for USB2 peripheral mode
20 One of the USB2 PHYs can be re-routed in peripheral mode to a DWC2 USB IP.
26 host-only mode.
33 - amlogic,meson-gxl-usb-ctrl
34 - amlogic,meson-gxm-usb-ctrl
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/sun/
Dcassini.h1 /* SPDX-License-Identifier: GPL-2.0+ */
29 /* cassini register map: 2M memory mapped in 32-bit memory space accessible as
30 * 32-bit words. there is no i/o port access. REG_ addresses are
41 /* this register sets the weights for the weighted round robin arbiter. e.g.,
42 * if rx weight == 1 and tx weight == 0, rx == 2x tx transfer credit
45 * DEFAULT: 0x0, SIZE: 5 bits
54 /* if enabled, BIM can send bursts across PCI bus > cacheline size. burst
57 * DEFAULT: 0x0, SIZE: 1 bit
62 /* top level interrupts [0-9] are auto-cleared to 0 when the status
63 * register is read. second level interrupts [13 - 18] are cleared at
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/sun/
Dcassini.h1 /* SPDX-License-Identifier: GPL-2.0+ */
29 /* cassini register map: 2M memory mapped in 32-bit memory space accessible as
30 * 32-bit words. there is no i/o port access. REG_ addresses are
41 /* this register sets the weights for the weighted round robin arbiter. e.g.,
42 * if rx weight == 1 and tx weight == 0, rx == 2x tx transfer credit
45 * DEFAULT: 0x0, SIZE: 5 bits
54 /* if enabled, BIM can send bursts across PCI bus > cacheline size. burst
57 * DEFAULT: 0x0, SIZE: 1 bit
62 /* top level interrupts [0-9] are auto-cleared to 0 when the status
63 * register is read. second level interrupts [13 - 18] are cleared at
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Dintel,dwmac-plat.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/intel,dwmac-plat.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
17 - intel,keembay-dwmac
19 - compatible
22 - $ref: snps,dwmac.yaml#
27 - items:
28 - enum:
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/intel/iwlegacy/
Dprph.h8 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
106 * processor is sleeping (e.g. for periodic power-saving shutdowns of radio).
119 * The uCode used for open-source drivers includes two programs:
121 * 1) Initialization -- performs hardware calibration and sets up some
128 * 2) Runtime/Protocol -- performs all normal runtime operations. This
170 * Data caching during power-downs:
172 * Just before the embedded controller powers down (e.g for automatic
173 * power-saving modes, or for RFKILL), uCode stores (via PCI busmaster DMA)
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/intel/iwlegacy/
Dprph.h8 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
106 * processor is sleeping (e.g. for periodic power-saving shutdowns of radio).
119 * The uCode used for open-source drivers includes two programs:
121 * 1) Initialization -- performs hardware calibration and sets up some
128 * 2) Runtime/Protocol -- performs all normal runtime operations. This
170 * Data caching during power-downs:
172 * Just before the embedded controller powers down (e.g for automatic
173 * power-saving modes, or for RFKILL), uCode stores (via PCI busmaster DMA)
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dintel,dwmac-plat.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/intel,dwmac-plat.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
17 - intel,keembay-dwmac
19 - compatible
22 - $ref: "snps,dwmac.yaml#"
27 - items:
28 - enum:
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/rockchip/
Drk3xxx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/soc/rockchip,boot-mode.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 interrupt-parent = <&gic>;
33 compatible = "fixed-clock";
34 clock-frequency = <24000000>;
35 #clock-cells = <0>;
[all …]
/kernel/linux/linux-6.6/drivers/usb/mtu3/
Dmtu3.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * mtu3.h - MediaTek USB3 DRD header
35 #define MU3D_EP_TXCR0(epnum) (U3D_TX1CSR0 + (((epnum) - 1) * 0x10))
36 #define MU3D_EP_TXCR1(epnum) (U3D_TX1CSR1 + (((epnum) - 1) * 0x10))
37 #define MU3D_EP_TXCR2(epnum) (U3D_TX1CSR2 + (((epnum) - 1) * 0x10))
39 #define MU3D_EP_RXCR0(epnum) (U3D_RX1CSR0 + (((epnum) - 1) * 0x10))
40 #define MU3D_EP_RXCR1(epnum) (U3D_RX1CSR1 + (((epnum) - 1) * 0x10))
41 #define MU3D_EP_RXCR2(epnum) (U3D_RX1CSR2 + (((epnum) - 1) * 0x10))
43 #define USB_QMU_TQHIAR(epnum) (U3D_TXQHIAR1 + (((epnum) - 1) * 0x4))
44 #define USB_QMU_RQHIAR(epnum) (U3D_RXQHIAR1 + (((epnum) - 1) * 0x4))
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
Dmain.h35 #define NTXRATE 64 /* # tx MPDUs rate is reported for */
48 * Usage example, e.g. a three-bit field (bits 4-6):
52 * regval = R_REG(osh, &regs->regfoo);
55 * W_REG(osh, &regs->regfoo, regval);
58 (((unsigned)1 << (width)) - 1)
67 /* max # supported core revisions (0 .. MAXCOREREV - 1) */
76 #define BRCMS_SHORTSLOT_AUTO -1 /* Driver will manage Shortslot setting */
91 #define TXFID_QUEUE_MASK 0x0007 /* Bits 0-2 */
92 #define TXFID_SEQ_MASK 0x7FE0 /* Bits 5-15 */
130 #define NFIFO 6 /* # tx/rx fifopairs */
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
Dmain.h35 #define NTXRATE 64 /* # tx MPDUs rate is reported for */
48 * Usage example, e.g. a three-bit field (bits 4-6):
52 * regval = R_REG(osh, &regs->regfoo);
55 * W_REG(osh, &regs->regfoo, regval);
58 (((unsigned)1 << (width)) - 1)
67 /* max # supported core revisions (0 .. MAXCOREREV - 1) */
76 #define BRCMS_SHORTSLOT_AUTO -1 /* Driver will manage Shortslot setting */
91 #define TXFID_QUEUE_MASK 0x0007 /* Bits 0-2 */
92 #define TXFID_SEQ_MASK 0x7FE0 /* Bits 5-15 */
130 #define NFIFO 6 /* # tx/rx fifopairs */
[all …]
/kernel/linux/linux-5.10/drivers/usb/mtu3/
Dmtu3.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * mtu3.h - MediaTek USB3 DRD header
32 #define MU3D_EP_TXCR0(epnum) (U3D_TX1CSR0 + (((epnum) - 1) * 0x10))
33 #define MU3D_EP_TXCR1(epnum) (U3D_TX1CSR1 + (((epnum) - 1) * 0x10))
34 #define MU3D_EP_TXCR2(epnum) (U3D_TX1CSR2 + (((epnum) - 1) * 0x10))
36 #define MU3D_EP_RXCR0(epnum) (U3D_RX1CSR0 + (((epnum) - 1) * 0x10))
37 #define MU3D_EP_RXCR1(epnum) (U3D_RX1CSR1 + (((epnum) - 1) * 0x10))
38 #define MU3D_EP_RXCR2(epnum) (U3D_RX1CSR2 + (((epnum) - 1) * 0x10))
40 #define USB_QMU_TQHIAR(epnum) (U3D_TXQHIAR1 + (((epnum) - 1) * 0x4))
41 #define USB_QMU_RQHIAR(epnum) (U3D_RXQHIAR1 + (((epnum) - 1) * 0x4))
[all …]
/kernel/linux/linux-6.6/arch/mips/boot/dts/ingenic/
Dx1830.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,tcu.h>
3 #include <dt-bindings/clock/ingenic,x1830-cgu.h>
4 #include <dt-bindings/dma/x1830-dma.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "ingenic,xburst-fpu2.0-mxu2.0";
21 clock-names = "cpu";
[all …]
Dx1000.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,tcu.h>
3 #include <dt-bindings/clock/ingenic,x1000-cgu.h>
4 #include <dt-bindings/dma/x1000-dma.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
21 clock-names = "cpu";
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/serial/
D8250.yaml3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - devicetree@vger.kernel.org
13 - $ref: /schemas/serial.yaml#
14 - if:
16 - aspeed,sirq-polarity-sense
20 const: aspeed,ast2500-vuart
21 - if:
24 const: mrvl,mmp-uart
27 reg-shift:
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/amlogic/
Dmeson.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/sound/meson-aiu.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 interrupt-parent = <&gic>;
15 iio-hwmon {
16 compatible = "iio-hwmon";
17 io-channels = <&saradc 8>;
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/serial/
D8250.yaml3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - devicetree@vger.kernel.org
13 - $ref: serial.yaml#
14 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
15 - if:
17 - required:
18 - aspeed,lpc-io-reg
19 - required:
20 - aspeed,lpc-interrupts
[all …]

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