Home
last modified time | relevance | path

Searched +full:gcc +full:- +full:ipq806x (Results 1 – 25 of 30) sorted by relevance

12

/kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/
Dqcom,ipq806x-usb-phy-hs.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,ipq806x-usb-phy-hs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm ipq806x usb DWC3 HS PHY CONTROLLER
10 - Ansuel Smith <ansuelsmth@gmail.com>
13 DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer
14 controllers used in ipq806x. Each DWC3 PHY controller should have its
19 const: qcom,ipq806x-usb-phy-hs
21 "#phy-cells":
[all …]
Dqcom,ipq806x-usb-phy-ss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,ipq806x-usb-phy-ss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm ipq806x usb DWC3 SS PHY CONTROLLER
10 - Ansuel Smith <ansuelsmth@gmail.com>
13 DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer
14 controllers used in ipq806x. Each DWC3 PHY controller should have its
19 const: qcom,ipq806x-usb-phy-ss
21 "#phy-cells":
[all …]
Dqcom-ipq806x-sata-phy.txt1 Qualcomm IPQ806x SATA PHY Controller
2 ------------------------------------
4 SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
8 - compatible: compatible list, contains "qcom,ipq806x-sata-phy"
9 - reg: offset and length of the SATA PHY register set;
10 - #phy-cells: must be zero
11 - clocks: must be exactly one entry
12 - clock-names: must be "cfg"
15 sata_phy: sata-phy@1b400000 {
16 compatible = "qcom,ipq806x-sata-phy";
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dqcom,ipq806x-usb-phy-hs.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,ipq806x-usb-phy-hs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm ipq806x usb DWC3 HS PHY CONTROLLER
10 - Ansuel Smith <ansuelsmth@gmail.com>
13 DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer
14 controllers used in ipq806x. Each DWC3 PHY controller should have its
19 const: qcom,ipq806x-usb-phy-hs
21 "#phy-cells":
[all …]
Dqcom,ipq806x-usb-phy-ss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,ipq806x-usb-phy-ss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm ipq806x usb DWC3 SS PHY CONTROLLER
10 - Ansuel Smith <ansuelsmth@gmail.com>
13 DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer
14 controllers used in ipq806x. Each DWC3 PHY controller should have its
19 const: qcom,ipq806x-usb-phy-ss
21 "#phy-cells":
[all …]
Dqcom-ipq806x-sata-phy.txt1 Qualcomm IPQ806x SATA PHY Controller
2 ------------------------------------
4 SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
8 - compatible: compatible list, contains "qcom,ipq806x-sata-phy"
9 - reg: offset and length of the SATA PHY register set;
10 - #phy-cells: must be zero
11 - clocks: must be exactly one entry
12 - clock-names: must be "cfg"
15 sata_phy: sata-phy@1b400000 {
16 compatible = "qcom,ipq806x-sata-phy";
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dqcom,gcc-ipq8064.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8064.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ansuel Smith <ansuelsmth@gmail.com>
17 include/dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
18 include/dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
21 - $ref: qcom,gcc.yaml#
26 - const: qcom,gcc-ipq8064
27 - const: syscon
[all …]
Dqcom,kpss-gcc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,kpss-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)
10 - Christian Marangi <ansuelsmth@gmail.com>
13 Krait Processor Sub-system (KPSS) Global Clock Controller (GCC). Used
15 to the kpss-gcc registers.
20 - enum:
21 - qcom,kpss-gcc-ipq8064
[all …]
Dqcom,kpss-acc-v1.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,kpss-acc-v1.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) v1
10 - Christian Marangi <ansuelsmth@gmail.com>
17 clock-controller for enabling the cpu and handling the aux clocks.
21 const: qcom,kpss-acc-v1
25 - description: Base address and size of the register region
26 - description: Optional base address and size of the alias register region
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/qcom/
Dqcom-ipq8064.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mfd/qcom-rpm.h>
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
8 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
11 #include <dt-bindings/soc/qcom,gsbi.h>
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mtd/
Dqcom,nandc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
15 - qcom,ipq806x-nand
16 - qcom,ipq4019-nand
17 - qcom,ipq6018-nand
18 - qcom,ipq8074-nand
19 - qcom,sdx55-nand
26 - description: Core Clock
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dqcom-ipq8064.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
6 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
9 #include <dt-bindings/soc/qcom,gsbi.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <1>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dipq806x-dwmac.txt1 * IPQ806x DWMAC Ethernet controller
8 - compatible: should be "qcom,ipq806x-gmac" along with "snps,dwmac"
12 - qcom,nss-common: should contain a phandle to a syscon device mapping the
13 nss-common registers.
15 - qcom,qsgmii-csr: should contain a phandle to a syscon device mapping the
16 qsgmii-csr registers.
22 compatible = "qcom,ipq806x-gmac";
25 interrupt-names = "macirq";
27 qcom,nss-common = <&nss_common>;
28 qcom,qsgmii-csr = <&qsgmii_csr>;
[all …]
Dqcom,ipq8064-mdio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/qcom,ipq8064-mdio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm ipq806x MDIO bus controller
10 - Ansuel Smith <ansuelsmth@gmail.com>
13 The ipq806x soc have a MDIO dedicated controller that is
17 - $ref: "mdio.yaml#"
21 const: qcom,ipq8064-mdio
30 - compatible
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Dipq806x-dwmac.txt1 * IPQ806x DWMAC Ethernet controller
8 - compatible: should be "qcom,ipq806x-gmac" along with "snps,dwmac"
12 - qcom,nss-common: should contain a phandle to a syscon device mapping the
13 nss-common registers.
15 - qcom,qsgmii-csr: should contain a phandle to a syscon device mapping the
16 qsgmii-csr registers.
22 compatible = "qcom,ipq806x-gmac";
25 interrupt-names = "macirq";
27 qcom,nss-common = <&nss_common>;
28 qcom,qsgmii-csr = <&qsgmii_csr>;
[all …]
Dqcom,ipq8064-mdio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/qcom,ipq8064-mdio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm ipq806x MDIO bus controller
10 - Ansuel Smith <ansuelsmth@gmail.com>
13 The ipq806x soc have a MDIO dedicated controller that is
17 - $ref: mdio.yaml#
21 const: qcom,ipq8064-mdio
30 - compatible
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/ata/
Dqcom-sata.txt3 SATA nodes are defined to describe on-chip Serial ATA controllers.
7 - compatible : compatible list, must contain "generic-ahci"
8 - interrupts : <interrupt mapping for SATA IRQ>
9 - reg : <registers mapping>
10 - phys : Must contain exactly one entry as specified
11 in phy-bindings.txt
12 - phy-names : Must be "sata-phy"
14 Required properties for "qcom,ipq806x-ahci" compatible:
15 - clocks : Must contain an entry for each entry in clock-names.
16 - clock-names : Shall be:
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/ata/
Dqcom-sata.txt3 SATA nodes are defined to describe on-chip Serial ATA controllers.
7 - compatible : compatible list, must contain "generic-ahci"
8 - interrupts : <interrupt mapping for SATA IRQ>
9 - reg : <registers mapping>
10 - phys : Must contain exactly one entry as specified
11 in phy-bindings.txt
12 - phy-names : Must be "sata-phy"
14 Required properties for "qcom,ipq806x-ahci" compatible:
15 - clocks : Must contain an entry for each entry in clock-names.
16 - clock-names : Shall be:
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dqcom,gcc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
18 - dt-bindings/clock/qcom,gcc-apq8084.h
19 - dt-bindings/reset/qcom,gcc-apq8084.h
20 - dt-bindings/clock/qcom,gcc-ipq4019.h
21 - dt-bindings/clock/qcom,gcc-ipq6018.h
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/dma/
Dqcom,adm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christian Marangi <ansuelsmth@gmail.com>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
27 "#dma-cells":
32 - description: phandle to the core clock
33 - description: phandle to the iface clock
35 clock-names:
37 - const: core
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/
Dqcom_nandc.txt4 - compatible: must be one of the following:
5 * "qcom,ipq806x-nand" - for EBI2 NAND controller being used in IPQ806x
7 * "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in
9 * "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in
12 - reg: MMIO address range
13 - clocks: must contain core clock and always on clock
14 - clock-names: must contain "core" for the core clock and "aon" for the
18 - dmas: DMA specifier, consisting of a phandle to the ADM DMA
21 - dma-names: must be "rxtx"
22 - qcom,cmd-crci: must contain the ADM command type CRCI block instance
[all …]
/kernel/linux/linux-5.10/drivers/clk/qcom/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_COMMON_CLK_QCOM) += clk-qcom.o
4 clk-qcom-y += common.o
5 clk-qcom-y += clk-regmap.o
6 clk-qcom-y += clk-alpha-pll.o
7 clk-qcom-y += clk-pll.o
8 clk-qcom-y += clk-rcg.o
9 clk-qcom-y += clk-rcg2.o
10 clk-qcom-y += clk-branch.o
11 clk-qcom-y += clk-regmap-divider.o
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/
Dqcom-soc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/qcom-soc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
15 qcom,SoC-IP
18 qcom,sdm845-llcc-bwmon
26 pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$"
28 - compatible
34 - pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+(pro)?-.*$"
[all …]
/kernel/linux/linux-6.6/drivers/clk/qcom/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_COMMON_CLK_QCOM) += clk-qcom.o
4 clk-qcom-y += common.o
5 clk-qcom-y += clk-regmap.o
6 clk-qcom-y += clk-alpha-pll.o
7 clk-qcom-y += clk-pll.o
8 clk-qcom-y += clk-rcg.o
9 clk-qcom-y += clk-rcg2.o
10 clk-qcom-y += clk-branch.o
11 clk-qcom-y += clk-regmap-divider.o
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/firmware/
Dqcom,scm.txt9 - compatible: must contain one of the following:
10 * "qcom,scm-apq8064"
11 * "qcom,scm-apq8084"
12 * "qcom,scm-ipq4019"
13 * "qcom,scm-ipq806x"
14 * "qcom,scm-ipq8074"
15 * "qcom,scm-msm8660"
16 * "qcom,scm-msm8916"
17 * "qcom,scm-msm8960"
18 * "qcom,scm-msm8974"
[all …]

12