| /kernel/linux/linux-5.10/drivers/clocksource/ |
| D | timer-microchip-pit64b.c | 54 * @gclk: PIT64B's generic clock
60 struct clk *gclk; member
165 clk_disable_unprepare(timer->gclk); in mchp_pit64b_clkevt_suspend()
175 clk_prepare_enable(timer->gclk); in mchp_pit64b_clkevt_resume()
210 * PIT64B timer may be fed by gclk or pclk. When gclk is used its rate has to
211 * be at least 3 times lower that pclk's rate. pclk rate is fixed, gclk rate
212 * could be changed via clock APIs. The chosen clock (pclk or gclk) could be
215 * This function, first tries to use GCLK by requesting the desired rate from
217 * requested rate. If PCLK/GCLK < 3 (condition requested by PIT64B hardware)
227 * | |-->gclk -->|-->| | +---------+ +-----+ |
[all …]
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| /kernel/linux/linux-6.6/drivers/clocksource/ |
| D | timer-microchip-pit64b.c | 54 * @gclk: PIT64B's generic clock
60 struct clk *gclk; member
139 clk_disable_unprepare(timer->gclk); in mchp_pit64b_suspend()
147 clk_prepare_enable(timer->gclk); in mchp_pit64b_resume()
261 * PIT64B timer may be fed by gclk or pclk. When gclk is used its rate has to
262 * be at least 3 times lower that pclk's rate. pclk rate is fixed, gclk rate
263 * could be changed via clock APIs. The chosen clock (pclk or gclk) could be
266 * This function, first tries to use GCLK by requesting the desired rate from
268 * requested rate. If PCLK/GCLK < 3 (condition requested by PIT64B hardware)
278 * | |-->gclk -->|-->| | +---------+ +-----+ |
[all …]
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| /kernel/linux/linux-6.6/sound/soc/atmel/ |
| D | mchp-spdifrx.c | 296 * @gclk: generic clock
306 struct clk *gclk; member
476 /* GCLK is enabled by runtime PM. */ in mchp_spdifrx_hw_params()
477 clk_disable_unprepare(dev->gclk); in mchp_spdifrx_hw_params()
479 ret = clk_set_min_rate(dev->gclk, params_rate(params) * in mchp_spdifrx_hw_params()
483 "unable to set gclk min rate: rate %u * ratio %u + 1\n", in mchp_spdifrx_hw_params()
486 clk_prepare_enable(dev->gclk); in mchp_spdifrx_hw_params()
489 ret = clk_prepare_enable(dev->gclk); in mchp_spdifrx_hw_params()
491 dev_err(dev->dev, "unable to enable gclk: %d\n", ret); in mchp_spdifrx_hw_params()
495 dev_dbg(dev->dev, "GCLK range min set to %d\n", in mchp_spdifrx_hw_params()
[all …]
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| D | mchp-spdiftx.c | 196 struct clk *gclk; member
485 /* GCLK is enabled by runtime PM. */ in mchp_spdiftx_hw_params()
486 clk_disable_unprepare(dev->gclk); in mchp_spdiftx_hw_params()
488 ret = clk_set_rate(dev->gclk, params_rate(params) * in mchp_spdiftx_hw_params()
492 "unable to change gclk rate to: rate %u * ratio %u\n", in mchp_spdiftx_hw_params()
496 ret = clk_prepare_enable(dev->gclk); in mchp_spdiftx_hw_params()
498 dev_err(dev->dev, "unable to enable gclk: %d\n", ret); in mchp_spdiftx_hw_params()
502 dev_dbg(dev->dev, "%s(): GCLK set to %d\n", __func__, in mchp_spdiftx_hw_params()
738 clk_disable_unprepare(spdiftx->gclk); in mchp_spdiftx_runtime_suspend()
755 ret = clk_prepare_enable(spdiftx->gclk); in mchp_spdiftx_runtime_resume()
[all …]
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| D | mchp-i2s-mcc.c | 242 struct clk *gclk; member
447 ret = mchp_i2s_mcc_clk_get_rate_diff(dev->gclk, clk_rate, in mchp_i2s_mcc_config_divs()
451 dev_err(dev->dev, "gclk error for rate %lu: %d", in mchp_i2s_mcc_config_divs()
455 dev_dbg(dev->dev, "found perfect rate on gclk: %lu\n", in mchp_i2s_mcc_config_divs()
483 best_clk == dev->pclk ? "pclk" : "gclk", in mchp_i2s_mcc_config_divs()
491 if (best_clk == dev->gclk) in mchp_i2s_mcc_config_divs()
702 ret = clk_set_rate(dev->gclk, rate); in mchp_i2s_mcc_hw_params()
705 "unable to set rate %lu to GCLK: %d\n", in mchp_i2s_mcc_hw_params()
710 ret = clk_prepare(dev->gclk); in mchp_i2s_mcc_hw_params()
712 dev_err(dev->dev, "unable to prepare GCLK: %d\n", ret); in mchp_i2s_mcc_hw_params()
[all …]
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| D | atmel-classd.c | 31 struct clk *gclk; member
130 err = clk_prepare_enable(dd->gclk); in atmel_classd_cpu_dai_startup()
365 clk_disable_unprepare(dd->gclk); in atmel_classd_cpu_dai_hw_params()
367 ret = clk_set_rate(dd->gclk, sample_rates[best].gclk_rate); in atmel_classd_cpu_dai_hw_params()
377 return clk_prepare_enable(dd->gclk); in atmel_classd_cpu_dai_hw_params()
387 clk_disable_unprepare(dd->gclk); in atmel_classd_cpu_dai_shutdown()
552 dd->gclk = devm_clk_get(dev, "gclk"); in atmel_classd_probe()
553 if (IS_ERR(dd->gclk)) { in atmel_classd_probe()
554 ret = PTR_ERR(dd->gclk); in atmel_classd_probe()
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| D | atmel-i2s.c | 200 struct clk *gclk; member
298 if (!dev->gclk) { in atmel_i2s_get_gck_param()
445 clk_disable_unprepare(dev->gclk); in atmel_i2s_switch_mck_generator()
455 ret = clk_set_rate(dev->gclk, gclk_rate); in atmel_i2s_switch_mck_generator()
459 ret = clk_prepare_enable(dev->gclk); in atmel_i2s_switch_mck_generator()
580 if (!dev->gclk) in atmel_i2s_sama5d2_mck_init()
594 return clk_set_parent(muxclk, dev->gclk); in atmel_i2s_sama5d2_mck_init()
665 dev->gclk = devm_clk_get(&pdev->dev, "gclk"); in atmel_i2s_probe()
666 if (IS_ERR(dev->gclk)) { in atmel_i2s_probe()
667 if (PTR_ERR(dev->gclk) == -EPROBE_DEFER) in atmel_i2s_probe()
[all …]
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| D | atmel-pdmic.c | 31 struct clk *gclk; member
111 ret = clk_prepare_enable(dd->gclk); in atmel_pdmic_cpu_dai_startup()
117 clk_disable_unprepare(dd->gclk); in atmel_pdmic_cpu_dai_startup()
141 clk_disable_unprepare(dd->gclk); in atmel_pdmic_cpu_dai_shutdown()
406 gclk_rate = clk_get_rate(dd->gclk); in atmel_pdmic_cpu_dai_hw_params()
527 u32 clk_min_rate = (u32)(clk_get_rate(dd->gclk) >> 8); in atmel_pdmic_get_sample_rate()
602 dd->gclk = devm_clk_get(dev, "gclk"); in atmel_pdmic_probe()
603 if (IS_ERR(dd->gclk)) { in atmel_pdmic_probe()
604 ret = PTR_ERR(dd->gclk); in atmel_pdmic_probe()
609 /* The gclk clock frequency must always be three times in atmel_pdmic_probe()
[all …]
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| D | mchp-pdmc.c | 111 struct clk *gclk; member
582 round_rate = clk_round_rate(dd->gclk, in mchp_pdmc_hw_params()
599 clk_disable_unprepare(dd->gclk); in mchp_pdmc_hw_params()
602 ret = clk_set_rate(dd->gclk, gclk_rate); in mchp_pdmc_hw_params()
603 clk_prepare_enable(dd->gclk); in mchp_pdmc_hw_params()
605 dev_err(comp->dev, "unable to set rate %lu to GCLK: %d\n", in mchp_pdmc_hw_params()
985 clk_disable_unprepare(dd->gclk); in mchp_pdmc_runtime_suspend()
1002 ret = clk_prepare_enable(dd->gclk); in mchp_pdmc_runtime_resume()
1014 clk_disable_unprepare(dd->gclk); in mchp_pdmc_runtime_resume()
1052 dd->gclk = devm_clk_get(dev, "gclk"); in mchp_pdmc_probe()
[all …]
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| /kernel/linux/linux-5.10/sound/soc/atmel/ |
| D | mchp-i2s-mcc.c | 234 struct clk *gclk; member
425 ret = mchp_i2s_mcc_clk_get_rate_diff(dev->gclk, clk_rate, in mchp_i2s_mcc_config_divs()
429 dev_err(dev->dev, "gclk error for rate %lu: %d", in mchp_i2s_mcc_config_divs()
433 dev_dbg(dev->dev, "found perfect rate on gclk: %lu\n", in mchp_i2s_mcc_config_divs()
461 best_clk == dev->pclk ? "pclk" : "gclk", in mchp_i2s_mcc_config_divs()
469 if (best_clk == dev->gclk) in mchp_i2s_mcc_config_divs()
657 ret = clk_set_rate(dev->gclk, rate); in mchp_i2s_mcc_hw_params()
660 "unable to set rate %lu to GCLK: %d\n", in mchp_i2s_mcc_hw_params()
665 ret = clk_prepare(dev->gclk); in mchp_i2s_mcc_hw_params()
667 dev_err(dev->dev, "unable to prepare GCLK: %d\n", ret); in mchp_i2s_mcc_hw_params()
[all …]
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| D | mchp-spdifrx.c | 237 struct clk *gclk; member
410 clk_disable_unprepare(dev->gclk); in mchp_spdifrx_hw_params()
413 ret = clk_set_min_rate(dev->gclk, params_rate(params) * in mchp_spdifrx_hw_params()
417 "unable to set gclk min rate: rate %u * ratio %u + 1\n", in mchp_spdifrx_hw_params()
421 ret = clk_prepare_enable(dev->gclk); in mchp_spdifrx_hw_params()
423 dev_err(dev->dev, "unable to enable gclk: %d\n", ret); in mchp_spdifrx_hw_params()
428 dev_dbg(dev->dev, "GCLK range min set to %d\n", in mchp_spdifrx_hw_params()
446 clk_disable_unprepare(dev->gclk); in mchp_spdifrx_hw_free()
650 * The RSR.ULOCK has wrong value if both pclk and gclk are enabled in mchp_spdifrx_ulock_get()
680 * The RSR.ULOCK has wrong value if both pclk and gclk are enabled in mchp_spdifrx_badf_get()
[all …]
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| D | atmel-classd.c | 31 struct clk *gclk; member
130 err = clk_prepare_enable(dd->gclk); in atmel_classd_cpu_dai_startup()
365 clk_disable_unprepare(dd->gclk); in atmel_classd_cpu_dai_hw_params()
367 ret = clk_set_rate(dd->gclk, sample_rates[best].gclk_rate); in atmel_classd_cpu_dai_hw_params()
377 return clk_prepare_enable(dd->gclk); in atmel_classd_cpu_dai_hw_params()
387 clk_disable_unprepare(dd->gclk); in atmel_classd_cpu_dai_shutdown()
553 dd->gclk = devm_clk_get(dev, "gclk"); in atmel_classd_probe()
554 if (IS_ERR(dd->gclk)) { in atmel_classd_probe()
555 ret = PTR_ERR(dd->gclk); in atmel_classd_probe()
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| D | atmel-i2s.c | 200 struct clk *gclk; member
298 if (!dev->gclk) { in atmel_i2s_get_gck_param()
445 clk_disable_unprepare(dev->gclk); in atmel_i2s_switch_mck_generator()
455 ret = clk_set_rate(dev->gclk, gclk_rate); in atmel_i2s_switch_mck_generator()
459 ret = clk_prepare_enable(dev->gclk); in atmel_i2s_switch_mck_generator()
578 if (!dev->gclk) in atmel_i2s_sama5d2_mck_init()
592 return clk_set_parent(muxclk, dev->gclk); in atmel_i2s_sama5d2_mck_init()
664 dev->gclk = devm_clk_get(&pdev->dev, "gclk"); in atmel_i2s_probe()
665 if (IS_ERR(dev->gclk)) { in atmel_i2s_probe()
666 if (PTR_ERR(dev->gclk) == -EPROBE_DEFER) in atmel_i2s_probe()
[all …]
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| D | atmel-pdmic.c | 31 struct clk *gclk; member
111 ret = clk_prepare_enable(dd->gclk); in atmel_pdmic_cpu_dai_startup()
117 clk_disable_unprepare(dd->gclk); in atmel_pdmic_cpu_dai_startup()
141 clk_disable_unprepare(dd->gclk); in atmel_pdmic_cpu_dai_shutdown()
406 gclk_rate = clk_get_rate(dd->gclk); in atmel_pdmic_cpu_dai_hw_params()
531 u32 clk_min_rate = (u32)(clk_get_rate(dd->gclk) >> 8); in atmel_pdmic_get_sample_rate()
606 dd->gclk = devm_clk_get(dev, "gclk"); in atmel_pdmic_probe()
607 if (IS_ERR(dd->gclk)) { in atmel_pdmic_probe()
608 ret = PTR_ERR(dd->gclk); in atmel_pdmic_probe()
613 /* The gclk clock frequency must always be three times in atmel_pdmic_probe()
[all …]
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| D | mchp-spdiftx.c | 197 struct clk *gclk; member
491 clk_disable_unprepare(dev->gclk); in mchp_spdiftx_hw_params()
494 ret = clk_set_rate(dev->gclk, params_rate(params) * in mchp_spdiftx_hw_params()
498 "unable to change gclk rate to: rate %u * ratio %u\n", in mchp_spdiftx_hw_params()
502 ret = clk_prepare_enable(dev->gclk); in mchp_spdiftx_hw_params()
504 dev_err(dev->dev, "unable to enable gclk: %d\n", ret); in mchp_spdiftx_hw_params()
508 dev_dbg(dev->dev, "%s(): GCLK set to %d\n", __func__, in mchp_spdiftx_hw_params()
528 clk_disable_unprepare(dev->gclk); in mchp_spdiftx_hw_free()
811 dev->gclk = devm_clk_get(&pdev->dev, "gclk"); in mchp_spdiftx_probe()
812 if (IS_ERR(dev->gclk)) { in mchp_spdiftx_probe()
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | emev2.dtsi | 78 compatible = "renesas,emev2-smu-gclk";
90 compatible = "renesas,emev2-smu-gclk";
127 compatible = "renesas,emev2-smu-gclk";
133 compatible = "renesas,emev2-smu-gclk";
139 compatible = "renesas,emev2-smu-gclk";
145 compatible = "renesas,emev2-smu-gclk";
151 compatible = "renesas,emev2-smu-gclk";
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/renesas/ |
| D | emev2.dtsi | 78 compatible = "renesas,emev2-smu-gclk";
90 compatible = "renesas,emev2-smu-gclk";
127 compatible = "renesas,emev2-smu-gclk";
133 compatible = "renesas,emev2-smu-gclk";
139 compatible = "renesas,emev2-smu-gclk";
145 compatible = "renesas,emev2-smu-gclk";
151 compatible = "renesas,emev2-smu-gclk";
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| /kernel/linux/linux-6.6/drivers/pwm/ |
| D | pwm-atmel-tcb.c | 56 struct clk *gclk; member
276 * If there is a gclk, the first divisor is actually the gclk selector in atmel_tcb_pwm_config()
278 if (tcbpwmc->gclk) in atmel_tcb_pwm_config()
431 tcbpwm->gclk = of_clk_get_by_name(np->parent, "gclk"); in atmel_tcb_pwm_probe()
432 if (IS_ERR(tcbpwm->gclk)) { in atmel_tcb_pwm_probe()
433 err = PTR_ERR(tcbpwm->gclk); in atmel_tcb_pwm_probe()
462 clk_put(tcbpwm->gclk); in atmel_tcb_pwm_probe()
480 clk_put(tcbpwm->gclk); in atmel_tcb_pwm_remove()
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/sound/ |
| D | atmel,sama5d2-i2s.yaml | 34 with gclk when Master Mode is required.
40 - const: gclk
82 clock-names = "pclk", "gclk", "muxclk";
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| D | microchip,sama7g5-spdifrx.yaml | 37 - const: gclk
72 clock-names = "pclk", "gclk";
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | renesas,emev2-smu.txt | 32 - compatible: Should be "renesas,emev2-smu-gclk"
47 compatible = "renesas,emev2-smu-gclk";
93 compatible = "renesas,emev2-smu-gclk";
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/ |
| D | mchp,spdifrx.yaml | 37 - const: gclk
72 clock-names = "pclk", "gclk";
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| D | mchp-i2s-mcc.txt | 16 - "gclk" (generated clock) Optional (1).
40 clock-names = "pclk", "gclk";
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| D | atmel-classd.txt | 16 Required elements: "pclk" and "gclk".
47 clock-names = "pclk", "gclk";
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| D | mchp,spdiftx.yaml | 37 - const: gclk
72 clock-names = "pclk", "gclk";
|