| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/gpio/ |
| D | xlnx,gpio-xilinx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/xlnx,gpio-xilinx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx AXI GPIO controller
10 - Neeli Srinivas <srinivas.neeli@amd.com>
13 The AXI GPIO design provides a general purpose input/output interface
14 to an AXI4-Lite interface. The AXI GPIO can be configured as either
15 a single or a dual-channel device. The width of each channel is
22 - xlnx,xps-gpio-1.00.a
[all …]
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| D | gpio-mmio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-mmio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic MMIO GPIO
10 - Linus Walleij <linus.walleij@linaro.org>
11 - Bartosz Golaszewski <brgl@bgdev.pl>
14 Some simple GPIO controllers may consist of a single data register or a pair
15 of set/clear-bit registers. Such controllers are common for glue logic in
16 FPGAs or ASICs. Commonly, these controllers are accessed over memory-mapped
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/auxdisplay/ |
| D | hit,hd44780.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert@linux-m68k.org>
15 interface, which can be used in either 4-bit or 8-bit mode. By using a
16 GPIO expander it is possible to use the driver with one of the popular I2C
24 data-gpios:
26 GPIO pins connected to the data signal lines DB0-DB7 (8-bit mode) or
27 DB4-DB7 (4-bit mode) of the LCD Controller's bus interface.
29 - maxItems: 4
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/gpio/ |
| D | gpio-xilinx.txt | 1 Xilinx plb/axi GPIO controller
3 Dual channel GPIO controller with configurable number of pins
9 - compatible : Should be "xlnx,xps-gpio-1.00.a"
10 - reg : Address and length of the register set for the device
11 - #gpio-cells : Should be two. The first cell is the pin number and the
13 - gpio-controller : Marks the device node as a GPIO controller.
16 - interrupts : Interrupt mapping for GPIO IRQ.
17 - xlnx,all-inputs : if n-th bit is setup, GPIO-n is input
18 - xlnx,dout-default : if n-th bit is 1, GPIO-n default value is 1
19 - xlnx,gpio-width : gpio width
[all …]
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| /kernel/linux/linux-6.6/drivers/gpio/ |
| D | gpio-xilinx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Xilinx gpio driver for xps/axi_gpio IP.
5 * Copyright 2008 - 2013 Xilinx, Inc.
12 #include <linux/gpio/driver.h>
35 /* Read/Write access to the GPIO registers */
45 * struct xgpio_instance - Stores information about GPIO device
46 * @gc: GPIO chip
48 * @hw_map: GPIO pin mapping on hardware side
49 * @sw_map: GPIO pin mapping on software side
50 * @state: GPIO write state shadow register
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/auxdisplay/ |
| D | hit,hd44780.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert@linux-m68k.org>
15 interface, which can be used in either 4-bit or 8-bit mode.
21 data-gpios:
23 GPIO pins connected to the data signal lines DB0-DB7 (8-bit mode) or
24 DB4-DB7 (4-bit mode) of the LCD Controller's bus interface.
26 - maxItems: 4
27 - maxItems: 8
[all …]
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| /kernel/linux/linux-5.10/arch/arm/mach-s3c/ |
| D | setup-sdhci-gpio-s3c24xx.c | 1 // SPDX-License-Identifier: GPL-2.0
6 // S3C2416 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
8 // Based on mach-s3c64xx/setup-sdhci-gpio.c
15 #include <linux/gpio.h>
17 #include "regs-gpio.h"
18 #include "gpio-samsung.h"
19 #include "gpio-cfg.h"
22 void s3c2416_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) in s3c2416_setup_sdhci0_cfg_gpio() argument
24 s3c_gpio_cfgrange_nopull(S3C2410_GPE(5), 2 + width, S3C_GPIO_SFN(2)); in s3c2416_setup_sdhci0_cfg_gpio()
27 void s3c2416_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) in s3c2416_setup_sdhci1_cfg_gpio() argument
[all …]
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| D | setup-sdhci-gpio-s3c64xx.c | 1 // SPDX-License-Identifier: GPL-2.0
7 // S3C64XX - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
14 #include <linux/gpio.h>
16 #include "gpio-cfg.h"
18 #include "gpio-samsung.h"
20 void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) in s3c64xx_setup_sdhci0_cfg_gpio() argument
22 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; in s3c64xx_setup_sdhci0_cfg_gpio()
24 /* Set all the necessary GPG pins to special-function 2 */ in s3c64xx_setup_sdhci0_cfg_gpio()
25 s3c_gpio_cfgrange_nopull(S3C64XX_GPG(0), 2 + width, S3C_GPIO_SFN(2)); in s3c64xx_setup_sdhci0_cfg_gpio()
27 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { in s3c64xx_setup_sdhci0_cfg_gpio()
[all …]
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| /kernel/linux/linux-6.6/drivers/pinctrl/actions/ |
| D | pinctrl-owl.h | 1 // SPDX-License-Identifier: GPL-2.0+
6 * Author: David Liu <liuwei@actions-semi.com>
18 #define MUX_PG(group_name, reg, shift, width) \ argument
27 .mfpctl_width = width, \
28 .drv_reg = -1, \
29 .drv_shift = -1, \
30 .drv_width = -1, \
31 .sr_reg = -1, \
32 .sr_shift = -1, \
33 .sr_width = -1, \
[all …]
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| D | pinctrl-owl.c | 1 // SPDX-License-Identifier: GPL-2.0+
6 * Author: David Liu <liuwei@actions-semi.com>
14 #include <linux/gpio/driver.h>
25 #include <linux/pinctrl/pinconf-generic.h>
31 #include "../pinctrl-utils.h"
32 #include "pinctrl-owl.h"
35 * struct owl_pinctrl - pinctrl state of the device
38 * @chip: gpio chip
70 u32 bit, u32 width) in owl_read_field() argument
74 tmp = readl_relaxed(pctrl->base + reg); in owl_read_field()
[all …]
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| /kernel/linux/linux-5.10/drivers/pinctrl/actions/ |
| D | pinctrl-owl.h | 1 // SPDX-License-Identifier: GPL-2.0+
6 * Author: David Liu <liuwei@actions-semi.com>
18 #define MUX_PG(group_name, reg, shift, width) \ argument
27 .mfpctl_width = width, \
28 .drv_reg = -1, \
29 .drv_shift = -1, \
30 .drv_width = -1, \
31 .sr_reg = -1, \
32 .sr_shift = -1, \
33 .sr_width = -1, \
[all …]
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| D | pinctrl-owl.c | 1 // SPDX-License-Identifier: GPL-2.0+
6 * Author: David Liu <liuwei@actions-semi.com>
14 #include <linux/gpio/driver.h>
24 #include <linux/pinctrl/pinconf-generic.h>
29 #include "../pinctrl-utils.h"
30 #include "pinctrl-owl.h"
33 * struct owl_pinctrl - pinctrl state of the device
36 * @chip: gpio chip
70 u32 bit, u32 width) in owl_read_field() argument
74 tmp = readl_relaxed(pctrl->base + reg); in owl_read_field()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpio/ |
| D | gpio-xilinx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Xilinx gpio driver for xps/axi_gpio IP.
5 * Copyright 2008 - 2013 Xilinx, Inc.
15 #include <linux/gpio/driver.h>
24 /* Read/Write access to the GPIO registers */
34 * struct xgpio_instance - Stores information about GPIO device
35 * @gc: GPIO chip
37 * @gpio_width: GPIO width for every channel
38 * @gpio_state: GPIO state shadow register
39 * @gpio_dir: GPIO direction shadow register
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/hisilicon/ |
| D | hikey970-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/pinctrl/hisi.h>
10 range: gpio-range {
11 #pinctrl-single,gpio-range-cells = <3>;
15 compatible = "pinctrl-single";
17 #pinctrl-cells = <1>;
18 #gpio-range-cells = <0x3>;
19 pinctrl-single,register-width = <0x20>;
20 pinctrl-single,function-mask = <0x7>;
21 /* pin base, nr pins & gpio function */
[all …]
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| /kernel/linux/linux-6.6/arch/arm/mach-s3c/ |
| D | setup-sdhci-gpio-s3c64xx.c | 1 // SPDX-License-Identifier: GPL-2.0
7 // S3C64XX - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
14 #include <linux/gpio.h>
16 #include "gpio-cfg.h"
18 #include "gpio-samsung.h"
20 void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) in s3c64xx_setup_sdhci0_cfg_gpio() argument
22 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; in s3c64xx_setup_sdhci0_cfg_gpio()
24 /* Set all the necessary GPG pins to special-function 2 */ in s3c64xx_setup_sdhci0_cfg_gpio()
25 s3c_gpio_cfgrange_nopull(S3C64XX_GPG(0), 2 + width, S3C_GPIO_SFN(2)); in s3c64xx_setup_sdhci0_cfg_gpio()
27 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { in s3c64xx_setup_sdhci0_cfg_gpio()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/ |
| D | gpio-control-nand.txt | 1 GPIO assisted NAND flash
3 The GPIO assisted NAND flash uses a memory mapped interface to
4 read/write the NAND commands and data and GPIO pins for the control
8 - compatible : "gpio-control-nand"
9 - reg : should specify localbus chip select and size used for the chip. The
12 - #address-cells, #size-cells : Must be present if the device has sub-nodes
14 - gpios : Specifies the GPIO pins to control the NAND device. The order of
15 GPIO references is: RDY, nCE, ALE, CLE, and nWP. nCE and nWP are optional.
18 - bank-width : Width (in bytes) of the device. If not present, the width
20 - chip-delay : chip dependent delay for transferring data from array to
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/mtd/ |
| D | gpio-control-nand.txt | 1 GPIO assisted NAND flash
3 The GPIO assisted NAND flash uses a memory mapped interface to
4 read/write the NAND commands and data and GPIO pins for the control
8 - compatible : "gpio-control-nand"
9 - reg : should specify localbus chip select and size used for the chip. The
12 - #address-cells, #size-cells : Must be present if the device has sub-nodes
14 - gpios : Specifies the GPIO pins to control the NAND device. The order of
15 GPIO references is: RDY, nCE, ALE, CLE, and nWP. nCE and nWP are optional.
18 - bank-width : Width (in bytes) of the device. If not present, the width
20 - chip-delay : chip dependent delay for transferring data from array to
[all …]
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| /kernel/linux/linux-6.6/tools/testing/selftests/gpio/ |
| D | gpio-mockup.sh | 1 #!/bin/bash -efu
2 # SPDX-License-Identifier: GPL-2.0
7 #4: skip test - including run as non-root user
13 module="gpio-mockup"
29 echo "$0 [-frv] [-t type]"
30 echo "-f: full test (minimal set run by default)"
31 echo "-r: test random lines as well as fence posts"
32 echo "-t: interface type:"
33 echo " cdev (character device ABI) - default"
36 echo "-v: verbose progress reporting"
[all …]
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| /kernel/linux/linux-6.6/arch/riscv/boot/dts/thead/ |
| D | th1520.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <1>;
16 #size-cells = <0>;
17 timebase-frequency = <3000000>;
24 i-cache-block-size = <64>;
25 i-cache-size = <65536>;
26 i-cache-sets = <512>;
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/ |
| D | pinctrl-single.txt | 1 One-register-per-pin type device tree based pinctrl driver
4 - compatible : "pinctrl-single" or "pinconf-single".
5 "pinctrl-single" means that pinconf isn't supported.
6 "pinconf-single" means that generic pinconf is supported.
8 - reg : offset and length of the register set for the mux registers
10 - #pinctrl-cells : number of cells in addition to the index, set to 1
11 for pinctrl-single,pins and 2 for pinctrl-single,bits
13 - pinctrl-single,register-width : pinmux register access width in bits
15 - pinctrl-single,function-mask : mask of allowed pinmux function bits
19 - pinctrl-single,function-off : function off mode for disabled state if
[all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/marvell/ |
| D | orion5x-rd88f5182-nas.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
4 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
7 #include "orion5x-mv88f5182.dtsi"
11 compatible = "marvell,rd-88f5182-nas", "marvell,orion5x-88f5182", "marvell,orion5x";
20 stdout-path = &uart0;
30 gpio-leds {
31 compatible = "gpio-leds";
32 pinctrl-0 = <&pmx_debug_led>;
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | orion5x-rd88f5182-nas.dts | 2 * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include "orion5x-mv88f5182.dtsi"
16 compatible = "marvell,rd-88f5182-nas", "marvell,orion5x-88f5182", "marvell,orion5x";
25 stdout-path = &uart0;
35 gpio-leds {
36 compatible = "gpio-leds";
37 pinctrl-0 = <&pmx_debug_led>;
38 pinctrl-names = "default";
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/bitmain/ |
| D | bm1880.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/clock/bm1880-clock.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/reset/bitmain,bm1880-reset.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a53";
[all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/bitmain/ |
| D | bm1880.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/clock/bm1880-clock.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/reset/bitmain,bm1880-reset.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a53";
[all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/nvidia/ |
| D | tegra234-p3701-0000.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
4 #include "tegra234-p3701.dtsi"
8 compatible = "nvidia,p3701-0000", "nvidia,tegra234";
19 vcc-supply = <&vdd_1v8_hs>;
20 address-width = <8>;
23 read-only;
31 compatible = "jedec,spi-nor";
33 spi-max-frequency = <102000000>;
34 spi-tx-bus-width = <4>;
35 spi-rx-bus-width = <4>;
[all …]
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