| /kernel/linux/linux-5.10/drivers/gpu/drm/sun4i/ |
| D | sun8i_hdmi_phy.c | 1 // SPDX-License-Identifier: GPL-2.0+
126 static int sun8i_hdmi_phy_config_a83t(struct dw_hdmi *hdmi, in sun8i_hdmi_phy_config_a83t() argument
127 struct sun8i_hdmi_phy *phy, in sun8i_hdmi_phy_config_a83t() argument
130 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG, in sun8i_hdmi_phy_config_a83t()
135 dw_hdmi_phy_gen2_txpwron(hdmi, 0); in sun8i_hdmi_phy_config_a83t()
136 dw_hdmi_phy_gen2_pddq(hdmi, 1); in sun8i_hdmi_phy_config_a83t()
138 dw_hdmi_phy_reset(hdmi); in sun8i_hdmi_phy_config_a83t()
140 dw_hdmi_phy_gen2_pddq(hdmi, 0); in sun8i_hdmi_phy_config_a83t()
142 dw_hdmi_phy_i2c_set_addr(hdmi, I2C_ADDR); in sun8i_hdmi_phy_config_a83t()
145 * Values are taken from BSP HDMI driver. Although AW didn't in sun8i_hdmi_phy_config_a83t()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/msm/ |
| D | hdmi.txt | 1 Qualcomm adreno/snapdragon hdmi output
4 - compatible: one of the following
5 * "qcom,hdmi-tx-8996"
6 * "qcom,hdmi-tx-8994"
7 * "qcom,hdmi-tx-8084"
8 * "qcom,hdmi-tx-8974"
9 * "qcom,hdmi-tx-8660"
10 * "qcom,hdmi-tx-8960"
11 - reg: Physical base address and length of the controller's registers
12 - reg-names: "core_physical"
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| /kernel/linux/linux-6.6/drivers/gpu/drm/sun4i/ |
| D | sun8i_hdmi_phy.c | 1 // SPDX-License-Identifier: GPL-2.0+
127 static void sun8i_hdmi_phy_set_polarity(struct sun8i_hdmi_phy *phy, in sun8i_hdmi_phy_set_polarity() argument
132 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in sun8i_hdmi_phy_set_polarity()
135 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in sun8i_hdmi_phy_set_polarity()
138 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG, in sun8i_hdmi_phy_set_polarity()
142 static int sun8i_a83t_hdmi_phy_config(struct dw_hdmi *hdmi, void *data, in sun8i_a83t_hdmi_phy_config() argument
146 unsigned int clk_rate = mode->crtc_clock * 1000; in sun8i_a83t_hdmi_phy_config()
147 struct sun8i_hdmi_phy *phy = data; in sun8i_a83t_hdmi_phy_config() local
149 sun8i_hdmi_phy_set_polarity(phy, mode); in sun8i_a83t_hdmi_phy_config()
151 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG, in sun8i_a83t_hdmi_phy_config()
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/ |
| D | amlogic,meson8-hdmi-tx-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/amlogic,meson8-hdmi-tx-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Amlogic Meson8, Meson8b and Meson8m2 HDMI TX PHY
10 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
13 The HDMI TX PHY node should be the child of a syscon node with the
16 compatible = "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon"
23 pattern: "^hdmi-phy@[0-9a-f]+$"
27 - items:
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| D | mediatek,hdmi-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek High Definition Multimedia Interface (HDMI) PHY
11 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
12 - Philipp Zabel <p.zabel@pengutronix.de>
13 - Chunfeng Yun <chunfeng.yun@mediatek.com>
16 The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
17 output and drives the HDMI pads.
[all …]
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| D | phy-rockchip-inno-hdmi.txt | 1 ROCKCHIP HDMI PHY WITH INNO IP BLOCK
4 - compatible : should be one of the listed compatibles:
5 * "rockchip,rk3228-hdmi-phy",
6 * "rockchip,rk3328-hdmi-phy";
7 - reg : Address and length of the hdmi phy control register set
8 - clocks : phandle + clock specifier for the phy clocks
9 - clock-names : string, clock name, must contain "sysclk" for system
10 control and register configuration, "refoclk" for crystal-
11 oscillator reference PLL clock input and "refpclk" for pclk-
13 - #clock-cells: should be 0.
[all …]
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| D | qcom,hdmi-phy-other.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $id: http://devicetree.org/schemas/phy/qcom,hdmi-phy-other.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Qualcomm Adreno/Snapdragon HDMI phy
11 - Rob Clark <robdclark@gmail.com>
16 - qcom,hdmi-phy-8660
17 - qcom,hdmi-phy-8960
18 - qcom,hdmi-phy-8974
19 - qcom,hdmi-phy-8084
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/exynos/ |
| D | exynos_hdmi.txt | 1 Device-Tree bindings for drm hdmi driver
4 - compatible: value should be one among the following:
5 1) "samsung,exynos4210-hdmi"
6 2) "samsung,exynos4212-hdmi"
7 3) "samsung,exynos5420-hdmi"
8 4) "samsung,exynos5433-hdmi"
9 - reg: physical base address of the hdmi and length of memory mapped
11 - interrupts: interrupt number to the cpu.
12 - hpd-gpios: following information about the hotplug gpio pin.
16 - ddc: phandle to the hdmi ddc node
[all …]
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| /kernel/linux/linux-6.6/drivers/phy/mediatek/ |
| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for the phy drivers.
6 obj-$(CONFIG_PHY_MTK_DP) += phy-mtk-dp.o
7 obj-$(CONFIG_PHY_MTK_PCIE) += phy-mtk-pcie.o
8 obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
9 obj-$(CONFIG_PHY_MTK_UFS) += phy-mtk-ufs.o
10 obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o
12 phy-mtk-hdmi-drv-y := phy-mtk-hdmi.o
13 phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt2701.o
14 phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt8173.o
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/ |
| D | allwinner,sun8i-a83t-hdmi-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-hdmi-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A83t HDMI PHY
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
19 - allwinner,sun8i-a83t-hdmi-phy
20 - allwinner,sun8i-h3-hdmi-phy
[all …]
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| D | allwinner,sun8i-a83t-dw-hdmi.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A83t DWC HDMI TX Encoder
10 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller
11 IP with Allwinner\'s own PHY IP. It supports audio and video outputs
14 These DT bindings follow the Synopsys DWC HDMI TX bindings defined
15 in bridge/synopsys,dw-hdmi.yaml with the following device-specific
19 - Chen-Yu Tsai <wens@csie.org>
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/ |
| D | allwinner,sun8i-a83t-hdmi-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-hdmi-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A83t HDMI PHY Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
19 - allwinner,sun8i-a83t-hdmi-phy
20 - allwinner,sun8i-h3-hdmi-phy
[all …]
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| D | allwinner,sun8i-a83t-dw-hdmi.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A83t DWC HDMI TX Encoder Device Tree Bindings
10 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller
11 IP with Allwinner\'s own PHY IP. It supports audio and video outputs
14 These DT bindings follow the Synopsys DWC HDMI TX bindings defined
16 the following device-specific properties.
19 - Chen-Yu Tsai <wens@csie.org>
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/msm/hdmi/ |
| D | hdmi.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
15 #include <linux/hdmi.h>
20 #include "hdmi.xml.h"
33 struct hdmi { struct
58 struct hdmi_phy *phy; member
67 /* the encoder we are hooked to (outside of hdmi block) */ argument
70 bool hdmi_mode; /* are we in hdmi mode? */ argument
109 struct hdmi *hdmi; member
114 void msm_hdmi_set_mode(struct hdmi *hdmi, bool power_on);
116 static inline void hdmi_write(struct hdmi *hdmi, u32 reg, u32 data) in hdmi_write() argument
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| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/hdmi/ |
| D | hdmi.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
15 #include <linux/hdmi.h>
20 #include "hdmi.xml.h"
33 struct hdmi { struct
58 struct hdmi_phy *phy; member
65 /* the encoder we are hooked to (outside of hdmi block) */ argument
68 bool hdmi_mode; /* are we in hdmi mode? */ argument
110 struct hdmi *hdmi; member
115 void msm_hdmi_set_mode(struct hdmi *hdmi, bool power_on);
117 static inline void hdmi_write(struct hdmi *hdmi, u32 reg, u32 data) in hdmi_write() argument
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | phy-rockchip-inno-hdmi.txt | 1 ROCKCHIP HDMI PHY WITH INNO IP BLOCK
4 - compatible : should be one of the listed compatibles:
5 * "rockchip,rk3228-hdmi-phy",
6 * "rockchip,rk3328-hdmi-phy";
7 - reg : Address and length of the hdmi phy control register set
8 - clocks : phandle + clock specifier for the phy clocks
9 - clock-names : string, clock name, must contain "sysclk" for system
10 control and register configuration, "refoclk" for crystal-
11 oscillator reference PLL clock input and "refpclk" for pclk-
13 - #clock-cells: should be 0.
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/samsung/ |
| D | samsung,exynos-hdmi.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC HDMI
10 - Inki Dae <inki.dae@samsung.com>
11 - Seung-Woo Kim <sw0312.kim@samsung.com>
12 - Kyungmin Park <kyungmin.park@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
18 - samsung,exynos4210-hdmi
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/mediatek/ |
| D | mediatek,hdmi.txt | 1 Mediatek HDMI Encoder
4 The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
8 - compatible: Should be "mediatek,<chip>-hdmi".
9 - the supported chips are mt2701, mt7623 and mt8173
10 - reg: Physical base address and length of the controller's registers
11 - interrupts: The interrupt signal from the function block.
12 - clocks: device clocks
13 See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
14 - clock-names: must contain "pixel", "pll", "bclk", and "spdif".
15 - phys: phandle link to the HDMI PHY node.
[all …]
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| /kernel/linux/linux-5.10/drivers/phy/mediatek/ |
| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for the phy drivers.
6 obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
7 obj-$(CONFIG_PHY_MTK_UFS) += phy-mtk-ufs.o
8 obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o
10 phy-mtk-hdmi-drv-y := phy-mtk-hdmi.o
11 phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt2701.o
12 phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt8173.o
13 obj-$(CONFIG_PHY_MTK_HDMI) += phy-mtk-hdmi-drv.o
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/bridge/synopsys/ |
| D | dw-hdmi.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DesignWare High-Definition Multimedia Interface (HDMI) driver
5 * Copyright (C) 2013-2015 Mentor Graphics Inc.
6 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
12 #include <linux/hdmi.h>
20 #include <linux/dma-mapping.h>
23 #include <media/cec-notifier.h>
25 #include <uapi/linux/media-bus-format.h>
38 #include "dw-hdmi-audio.h"
39 #include "dw-hdmi-cec.h"
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/bridge/synopsys/ |
| D | dw-hdmi.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DesignWare High-Definition Multimedia Interface (HDMI) driver
5 * Copyright (C) 2013-2015 Mentor Graphics Inc.
6 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
12 #include <linux/hdmi.h>
19 #include <linux/dma-mapping.h>
22 #include <media/cec-notifier.h>
24 #include <uapi/linux/media-bus-format.h>
37 #include "dw-hdmi-audio.h"
38 #include "dw-hdmi-cec.h"
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/msm/ |
| D | qcom,mdss.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
11 - Rob Clark <robdclark@gmail.com>
15 encapsulates sub-blocks like MDP5, DSI, HDMI, eDP, etc.
19 pattern: "^display-subsystem@[0-9a-f]+$"
23 - qcom,mdss
29 reg-names:
32 - const: mdss_phys
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/rockchip/ |
| D | dw_hdmi-rockchip.txt | 1 Rockchip DWC HDMI TX Encoder
4 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
5 with a companion PHY IP.
7 These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
9 following device-specific properties.
14 - compatible: should be one of the following:
15 "rockchip,rk3228-dw-hdmi"
16 "rockchip,rk3288-dw-hdmi"
17 "rockchip,rk3328-dw-hdmi"
18 "rockchip,rk3399-dw-hdmi"
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/sti/ |
| D | sti_hdmi_tx3g4c28phy.c | 1 // SPDX-License-Identifier: GPL-2.0
70 * sti_hdmi_tx3g4c28phy_start - Start hdmi phy macro cell tx3g4c28
72 * @hdmi: pointer on the hdmi internal structure
76 static bool sti_hdmi_tx3g4c28phy_start(struct sti_hdmi *hdmi) in sti_hdmi_tx3g4c28phy_start() argument
78 u32 ckpxpll = hdmi->mode.clock * 1000; in sti_hdmi_tx3g4c28phy_start()
114 * Configure and power up the PHY PLL in sti_hdmi_tx3g4c28phy_start()
116 hdmi->event_received = false; in sti_hdmi_tx3g4c28phy_start()
118 hdmi_write(hdmi, (pllctrl | PLL_CFG_EN), HDMI_SRZ_PLL_CFG); in sti_hdmi_tx3g4c28phy_start()
121 wait_event_interruptible_timeout(hdmi->wait_event, in sti_hdmi_tx3g4c28phy_start()
122 hdmi->event_received == true, in sti_hdmi_tx3g4c28phy_start()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/sti/ |
| D | sti_hdmi_tx3g4c28phy.c | 1 // SPDX-License-Identifier: GPL-2.0
70 * Start hdmi phy macro cell tx3g4c28
72 * @hdmi: pointer on the hdmi internal structure
76 static bool sti_hdmi_tx3g4c28phy_start(struct sti_hdmi *hdmi) in sti_hdmi_tx3g4c28phy_start() argument
78 u32 ckpxpll = hdmi->mode.clock * 1000; in sti_hdmi_tx3g4c28phy_start()
114 * Configure and power up the PHY PLL in sti_hdmi_tx3g4c28phy_start()
116 hdmi->event_received = false; in sti_hdmi_tx3g4c28phy_start()
118 hdmi_write(hdmi, (pllctrl | PLL_CFG_EN), HDMI_SRZ_PLL_CFG); in sti_hdmi_tx3g4c28phy_start()
121 wait_event_interruptible_timeout(hdmi->wait_event, in sti_hdmi_tx3g4c28phy_start()
122 hdmi->event_received == true, in sti_hdmi_tx3g4c28phy_start()
[all …]
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