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Searched +full:hip06 +full:- +full:lpc (Results 1 – 8 of 8) sorted by relevance

/kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/hisilicon/
Dlow-pin-count.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/hisilicon/low-pin-count.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Hisilicon HiP06 Low Pin Count device
10 - Wei Xu <xuwei5@hisilicon.com>
13 Hisilicon HiP06 SoCs implement a Low Pin Count (LPC) controller, which
15 HiP06 is based on arm64 architecture where there is no I/O space. So, the
17 LPC device node.
21 pattern: '^isa@[0-9a-f]+$'
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/hisilicon/
Dlow-pin-count.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/hisilicon/low-pin-count.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Hisilicon HiP06 Low Pin Count device
10 - Wei Xu <xuwei5@hisilicon.com>
13 Hisilicon HiP06 SoCs implement a Low Pin Count (LPC) controller, which
15 HiP06 is based on arm64 architecture where there is no I/O space. So, the
17 LPC device node.
21 pattern: '^isa@[0-9a-f]+$'
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/hisilicon/
Dhip06.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip06-d03";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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Dhip07.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
/kernel/linux/linux-6.6/drivers/bus/
Dhisi_lpc.c1 // SPDX-License-Identifier: GPL-2.0+
22 #define DRV_NAME "hisi-lpc"
50 #define LPC_REG_OP_LEN 0x10 /* LPC cycles count per start */
58 /* The minimal nanosecond interval for each query on LPC cycle status */
66 * for extra 256 lpc clocks, so (256 + 13) * 30ns = 8 us. The maximum burst
84 return (status & LPC_REG_OP_STATUS_FINISHED) ? 0 : -EIO; in wait_lpc_idle()
86 } while (--waitcnt); in wait_lpc_idle()
88 return -ETIMEDOUT; in wait_lpc_idle()
92 * hisi_lpc_target_in - trigger a series of LPC cycles for read operation
93 * @lpcdev: pointer to hisi lpc device
[all …]
/kernel/linux/linux-5.10/drivers/bus/
Dhisi_lpc.c1 // SPDX-License-Identifier: GPL-2.0+
22 #define DRV_NAME "hisi-lpc"
50 #define LPC_REG_OP_LEN 0x10 /* LPC cycles count per start */
58 /* The minimal nanosecond interval for each query on LPC cycle status */
66 * for extra 256 lpc clocks, so (256 + 13) * 30ns = 8 us. The maximum burst
84 return (status & LPC_REG_OP_STATUS_FINISHED) ? 0 : -EIO; in wait_lpc_idle()
86 } while (--waitcnt); in wait_lpc_idle()
88 return -ETIME; in wait_lpc_idle()
92 * hisi_lpc_target_in - trigger a series of LPC cycles for read operation
93 * @lpcdev: pointer to hisi lpc device
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/hisilicon/
Dhip06.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip06-d03";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
Dhip07.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]