Home
last modified time | relevance | path

Searched +full:hpd +full:- +full:reliable +full:- +full:delay +full:- +full:ms (Results 1 – 13 of 13) sorted by relevance

/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/panel/
Dpanel-edp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-edp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Douglas Anderson <dianders@chromium.org>
14 to a Embedded DisplayPort AUX bus (see display/dp-aux-bus.yaml) without
17 board, either for second-sourcing purposes or to support multiple SKUs
51 :<T1>:<T2>: :<--T10-->:<T11>:<T12>:
52 : +-----------------------+---------+---------+
53 eDP -----------+ Black video | Src vid | Blk vid +
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/panel/
Dpanel-edp.c17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 #include <linux/delay.h>
46 * struct panel_delay - Describes delays for a simple panel.
50 * @hpd_reliable: Time for HPD to be reliable
53 * before the HPD signal is reliable. Ideally this is 0 but some panels,
57 * Presumably some old panels simply didn't have HPD hooked up and put
59 * hpd_absent. While that works, it's non-ideal.
64 * @hpd_absent: Time to wait if HPD isn't hooked up.
66 * Add this to the prepare delay if we know Hot Plug Detect isn't used.
68 * This is T3-max on eDP timing diagrams or the delay from power on
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/hdmi/
Dhdmi_hpd.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/delay.h>
65 const struct hdmi_platform_config *config = hdmi->config; in enable_hpd_clocks()
66 struct device *dev = &hdmi->pdev->dev; in enable_hpd_clocks()
70 for (i = 0; i < config->hpd_clk_cnt; i++) { in enable_hpd_clocks()
71 if (config->hpd_freq && config->hpd_freq[i]) { in enable_hpd_clocks()
72 ret = clk_set_rate(hdmi->hpd_clks[i], in enable_hpd_clocks()
73 config->hpd_freq[i]); in enable_hpd_clocks()
77 config->hpd_clk_names[i], ret); in enable_hpd_clocks()
80 ret = clk_prepare_enable(hdmi->hpd_clks[i]); in enable_hpd_clocks()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/hdmi/
Dhdmi_hpd.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/delay.h>
65 const struct hdmi_platform_config *config = hdmi->config; in enable_hpd_clocks()
66 struct device *dev = &hdmi->pdev->dev; in enable_hpd_clocks()
70 for (i = 0; i < config->hpd_clk_cnt; i++) { in enable_hpd_clocks()
71 if (config->hpd_freq && config->hpd_freq[i]) { in enable_hpd_clocks()
72 ret = clk_set_rate(hdmi->hpd_clks[i], in enable_hpd_clocks()
73 config->hpd_freq[i]); in enable_hpd_clocks()
77 config->hpd_clk_names[i], ret); in enable_hpd_clocks()
80 ret = clk_prepare_enable(hdmi->hpd_clks[i]); in enable_hpd_clocks()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/bridge/
Dti-sn65dsi86.c1 // SPDX-License-Identifier: GPL-2.0
134 * struct ti_sn65dsi86 - Platform data for ti-sn65dsi86 driver.
135 * @bridge_aux: AUX-bus sub device for MIPI-to-eDP bridge functionality.
136 * @gpio_aux: AUX-bus sub device for GPIO controller functionality.
137 * @aux_aux: AUX-bus sub device for eDP AUX channel functionality.
138 * @pwm_aux: AUX-bus sub device for PWM controller functionality.
153 * @ln_polrs: Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG.
159 * serves double-duty of keeping track of the direction and
165 * each other's read-modify-write.
230 ret = regmap_bulk_read(pdata->regmap, reg, buf, ARRAY_SIZE(buf)); in ti_sn65dsi86_read_u16()
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/qcom/
Dsdm845-cheza.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
26 stdout-path = "serial0:115200n8";
30 compatible = "pwm-backlight";
32 enable-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
33 power-supply = <&ppvar_sys>;
34 pinctrl-names = "default";
35 pinctrl-0 = <&ap_edp_bklten>;
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/qcom/
Dsdm845-cheza.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
25 stdout-path = "serial0:115200n8";
29 compatible = "pwm-backlight";
31 enable-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
32 power-supply = <&ppvar_sys>;
33 pinctrl-names = "default";
34 pinctrl-0 = <&ap_edp_bklten>;
37 /* FIXED REGULATORS - parents above children */
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
Dintel_dp.c107 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
119 return dig_port->base.type == INTEL_OUTPUT_EDP; in intel_dp_is_edp()
127 return crtc_state->port_clock >= 1000000; in intel_dp_is_uhbr()
132 intel_dp->sink_rates[0] = 162000; in intel_dp_set_default_sink_rates()
133 intel_dp->num_sink_rates = 1; in intel_dp_set_default_sink_rates()
145 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) { in intel_dp_set_dpcd_sink_rates()
149 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates)); in intel_dp_set_dpcd_sink_rates()
150 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates); in intel_dp_set_dpcd_sink_rates()
158 max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]); in intel_dp_set_dpcd_sink_rates()
159 max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps); in intel_dp_set_dpcd_sink_rates()
[all …]
Dintel_psr.c44 * Since Haswell Display controller supports Panel Self-Refresh on display
58 * The implementation uses the hardware-based PSR support which automatically
59 * enters/exits self-refresh mode. The hardware takes care of sending the
62 * changes to know when to exit self-refresh mode again. Unfortunately that
67 * issues the self-refresh re-enable code is done from a work queue, which
75 * entry/exit allows the HW to enter a low-power state even when page flipping
91 * EDP_PSR_DEBUG[16]/EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (hsw-skl):
155 * In standby mode (as opposed to link-off) this makes no difference
169 * The rest of the bits are more self-explanatory and/or
175 struct intel_connector *connector = intel_dp->attached_connector; in psr_global_enabled()
[all …]
Dintel_ddi.c96 level = intel_bios_hdmi_level_shift(encoder->devdata); in intel_ddi_hdmi_level()
98 level = trans->hdmi_default_entry; in intel_ddi_hdmi_level()
121 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_prepare_dp_ddi_buffers()
124 enum port port = encoder->port; in hsw_prepare_dp_ddi_buffers()
127 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in hsw_prepare_dp_ddi_buffers()
128 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) in hsw_prepare_dp_ddi_buffers()
133 intel_bios_dp_boost_level(encoder->devdata)) in hsw_prepare_dp_ddi_buffers()
138 trans->entries[i].hsw.trans1 | iboost_bit); in hsw_prepare_dp_ddi_buffers()
140 trans->entries[i].hsw.trans2); in hsw_prepare_dp_ddi_buffers()
152 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_prepare_hdmi_ddi_buffers()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
Dintel_psr.c38 * Since Haswell Display controller supports Panel Self-Refresh on display
52 * The implementation uses the hardware-based PSR support which automatically
53 * enters/exits self-refresh mode. The hardware takes care of sending the
56 * changes to know when to exit self-refresh mode again. Unfortunately that
61 * issues the self-refresh re-enable code is done from a work queue, which
69 * entry/exit allows the HW to enter a low-power state even when page flipping
84 switch (i915->psr.debug & I915_PSR_DEBUG_MODE_MASK) { in psr_global_enabled()
86 return i915->params.enable_psr; in psr_global_enabled()
98 drm_WARN_ON(&dev_priv->drm, crtc_state->dsc.compression_enable && in intel_psr2_enabled()
99 crtc_state->has_psr2); in intel_psr2_enabled()
[all …]
Dintel_ddi.c54 u32 trans1; /* balance leg enable, de-emph level */
360 /* BSpec has 2 recommended values - entries 0 and 8.
592 /* Voltage swing pre-emphasis */
606 /* Voltage swing pre-emphasis */
620 /* HDMI Preset VS Pre-emph */
626 { 0x3A, 0x0, 0x5 }, /* 6 Full -1.5 dB */
627 { 0x39, 0x0, 0x6 }, /* 7 Full -1.8 dB */
628 { 0x38, 0x0, 0x7 }, /* 8 Full -2 dB */
629 { 0x37, 0x0, 0x8 }, /* 9 Full -2.5 dB */
630 { 0x36, 0x0, 0x9 }, /* 10 Full -3 dB */
[all …]
Dintel_display.c2 * Copyright © 2006-2007 Intel Corporation
29 #include <linux/intel-iommu.h>
32 #include <linux/dma-resv.h>
208 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != in vlv_get_cck_clock()
222 if (dev_priv->hpll_freq == 0) in vlv_get_cck_clock_hpll()
223 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); in vlv_get_cck_clock_hpll()
225 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); in vlv_get_cck_clock_hpll()
237 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", in intel_update_czclk()
240 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", in intel_update_czclk()
241 dev_priv->czclk_freq); in intel_update_czclk()
[all …]