| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | qcom,usb-hsic-phy.txt | 1 Qualcomm's USB HSIC PHY
5 - compatible:
8 Definition: Should contain "qcom,usb-hsic-phy" and more specifically one of the
11 "qcom,usb-hsic-phy-mdm9615"
12 "qcom,usb-hsic-phy-msm8974"
14 - #phy-cells:
19 - clocks:
21 Value type: <prop-encoded-array>
22 Definition: Should contain clock specifier for phy, calibration and
25 - clock-names:
[all …]
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| D | allwinner,sun9i-a80-usb-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun9i-a80-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A80 USB PHY Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
18 const: allwinner,sun9i-a80-usb-phy
25 - description: Main PHY Clock
[all …]
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| D | nvidia,tegra124-xusb-padctl.txt | 11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
29 abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
34 --------------------
[all …]
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| D | marvell,mmp3-hsic-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0-or-later
4 ---
5 $id: "http://devicetree.org/schemas/phy/marvell,mmp3-hsic-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Marvell MMP3 HSIC PHY
11 - Lubomir Rintel <lkundrak@v3.sk>
15 const: marvell,mmp3-hsic-phy
21 reset-gpios:
25 "#phy-cells":
29 - compatible
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/ |
| D | allwinner,sun9i-a80-usb-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun9i-a80-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A80 USB PHY
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
18 const: allwinner,sun9i-a80-usb-phy
25 - maxItems: 1
[all …]
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| D | qcom,usb-hsic-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,usb-hsic-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm USB HSIC PHY Controller
10 - Bjorn Andersson <andersson@kernel.org>
11 - Vinod Koul <vkoul@kernel.org>
16 - enum:
17 - qcom,usb-hsic-phy-mdm9615
18 - qcom,usb-hsic-phy-msm8974
[all …]
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| D | marvell,mmp3-hsic-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/marvell,mmp3-hsic-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Marvell MMP3 HSIC PHY
11 - Lubomir Rintel <lkundrak@v3.sk>
15 const: marvell,mmp3-hsic-phy
21 "#phy-cells":
25 - compatible
26 - reg
[all …]
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| D | nvidia,tegra124-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
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| D | nvidia,tegra186-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
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| D | nvidia,tegra210-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
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| /kernel/linux/linux-6.6/drivers/phy/marvell/ |
| D | phy-pxa-28nm-hsic.c | 1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <linux/phy/phy.h>
42 struct phy *phy; member
56 static int mv_hsic_phy_init(struct phy *phy) in mv_hsic_phy_init() argument
58 struct mv_hsic_phy *mv_phy = phy_get_drvdata(phy); in mv_hsic_phy_init()
59 struct platform_device *pdev = mv_phy->pdev; in mv_hsic_phy_init()
60 void __iomem *base = mv_phy->base; in mv_hsic_phy_init()
63 clk_prepare_enable(mv_phy->clk); in mv_hsic_phy_init()
76 /* Make sure PHY PLL is locked */ in mv_hsic_phy_init()
80 dev_err(&pdev->dev, "HSIC PHY PLL not locked after 100mS."); in mv_hsic_phy_init()
[all …]
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| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Marvell platforms
6 bool "Armada 375 USB cluster PHY support" if COMPILE_TEST
12 tristate "Marvell Berlin SATA PHY driver"
17 Enable this to support the SATA PHY on Marvell Berlin SoCs.
20 tristate "Marvell Berlin USB PHY Driver"
25 Enable this to support the USB PHY on Marvell Berlin SoCs.
46 Enable this to support Marvell A3700 UTMI PHY driver.
76 Enable this to support Marvell CP110 UTMI PHY driver.
85 tristate "Marvell USB HSIC 28nm PHY Driver"
[all …]
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| D | phy-mmp3-hsic.c | 1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/phy/phy.h>
17 static int mmp3_hsic_phy_init(struct phy *phy) in mmp3_hsic_phy_init() argument
19 void __iomem *base = (void __iomem *)phy_get_drvdata(phy); in mmp3_hsic_phy_init()
36 { .compatible = "marvell,mmp3-hsic-phy", },
43 struct device *dev = &pdev->dev; in mmp3_hsic_phy_probe()
46 struct phy *phy; in mmp3_hsic_phy_probe() local
52 phy = devm_phy_create(dev, NULL, &mmp3_hsic_phy_ops); in mmp3_hsic_phy_probe()
53 if (IS_ERR(phy)) { in mmp3_hsic_phy_probe()
54 dev_err(dev, "failed to create PHY\n"); in mmp3_hsic_phy_probe()
[all …]
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| /kernel/linux/linux-5.10/drivers/phy/marvell/ |
| D | phy-pxa-28nm-hsic.c | 1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <linux/phy/phy.h>
42 struct phy *phy; member
56 static int mv_hsic_phy_init(struct phy *phy) in mv_hsic_phy_init() argument
58 struct mv_hsic_phy *mv_phy = phy_get_drvdata(phy); in mv_hsic_phy_init()
59 struct platform_device *pdev = mv_phy->pdev; in mv_hsic_phy_init()
60 void __iomem *base = mv_phy->base; in mv_hsic_phy_init()
63 clk_prepare_enable(mv_phy->clk); in mv_hsic_phy_init()
76 /* Make sure PHY PLL is locked */ in mv_hsic_phy_init()
80 dev_err(&pdev->dev, "HSIC PHY PLL not locked after 100mS."); in mv_hsic_phy_init()
[all …]
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| /kernel/linux/linux-6.6/drivers/phy/tegra/ |
| D | xusb-tegra124.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/phy/phy.h>
229 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_enable()
231 if (padctl->enable++ > 0) in tegra124_xusb_padctl_enable()
251 mutex_unlock(&padctl->lock); in tegra124_xusb_padctl_enable()
259 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_disable()
261 if (WARN_ON(padctl->enable == 0)) in tegra124_xusb_padctl_disable()
264 if (--padctl->enable > 0) in tegra124_xusb_padctl_disable()
284 mutex_unlock(&padctl->lock); in tegra124_xusb_padctl_disable()
297 return -ENODEV; in tegra124_usb3_save_context()
[all …]
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| D | xusb.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
12 #include <linux/phy/phy.h>
13 #include <linux/phy/tegra/xusb.h>
24 static struct phy *tegra_xusb_pad_of_xlate(struct device *dev, in tegra_xusb_pad_of_xlate()
28 struct phy *phy = NULL; in tegra_xusb_pad_of_xlate() local
31 if (args->args_count != 0) in tegra_xusb_pad_of_xlate()
32 return ERR_PTR(-EINVAL); in tegra_xusb_pad_of_xlate()
34 for (i = 0; i < pad->soc->num_lanes; i++) { in tegra_xusb_pad_of_xlate()
35 if (!pad->lanes[i]) in tegra_xusb_pad_of_xlate()
[all …]
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| /kernel/linux/linux-5.10/drivers/phy/tegra/ |
| D | xusb-tegra124.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/phy/phy.h>
229 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_enable()
231 if (padctl->enable++ > 0) in tegra124_xusb_padctl_enable()
251 mutex_unlock(&padctl->lock); in tegra124_xusb_padctl_enable()
259 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_disable()
261 if (WARN_ON(padctl->enable == 0)) in tegra124_xusb_padctl_disable()
264 if (--padctl->enable > 0) in tegra124_xusb_padctl_disable()
284 mutex_unlock(&padctl->lock); in tegra124_xusb_padctl_disable()
297 return -ENODEV; in tegra124_usb3_save_context()
[all …]
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| D | xusb-tegra210.c | 1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <linux/phy/phy.h>
25 ((x) ? (11 + ((x) - 1) * 6) : 0)
259 /* must be called under padctl->lock */
262 struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(padctl->pcie); in tegra210_pex_uphy_enable()
267 if (pcie->enable > 0) { in tegra210_pex_uphy_enable()
268 pcie->enable++; in tegra210_pex_uphy_enable()
272 err = clk_prepare_enable(pcie->pll); in tegra210_pex_uphy_enable()
276 err = reset_control_deassert(pcie->rst); in tegra210_pex_uphy_enable()
355 err = -ETIMEDOUT; in tegra210_pex_uphy_enable()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mfd/ |
| D | omap-usb-host.txt | 5 - compatible: should be "ti,usbhs-host"
6 - reg: should contain one register range i.e. start and length
7 - ti,hwmods: must contain "usb_host_hs"
11 - num-ports: number of USB ports. Usually this is automatically detected
15 - portN-mode: String specifying the port mode for port N, where N can be
18 "ehci-phy",
19 "ehci-tll",
20 "ehci-hsic",
21 "ohci-phy-6pin-datse0",
22 "ohci-phy-6pin-dpdm",
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/mfd/ |
| D | omap-usb-host.txt | 5 - compatible: should be "ti,usbhs-host"
6 - reg: should contain one register range i.e. start and length
7 - ti,hwmods: must contain "usb_host_hs"
11 - num-ports: number of USB ports. Usually this is automatically detected
15 - portN-mode: String specifying the port mode for port N, where N can be
18 "ehci-phy",
19 "ehci-tll",
20 "ehci-hsic",
21 "ohci-phy-6pin-datse0",
22 "ohci-phy-6pin-dpdm",
[all …]
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| /kernel/linux/linux-6.6/drivers/phy/samsung/ |
| D | phy-exynos5250-usb2.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 5250 support
11 #include <linux/phy/phy.h>
13 #include "phy-samsung-usb2.h"
15 /* Exynos USB PHY registers */
139 * can be written to the phy register.
168 return -EINVAL; in exynos5250_rate_to_clk()
176 struct samsung_usb2_phy_driver *drv = inst->drv; in exynos5250_isol()
180 if (drv->cfg == &exynos5250_usb2_phy_config && in exynos5250_isol()
181 inst->cfg->id == EXYNOS5250_DEVICE) in exynos5250_isol()
[all …]
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| /kernel/linux/linux-5.10/drivers/phy/samsung/ |
| D | phy-exynos5250-usb2.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 5250 support
11 #include <linux/phy/phy.h>
13 #include "phy-samsung-usb2.h"
15 /* Exynos USB PHY registers */
140 * can be written to the phy register.
169 return -EINVAL; in exynos5250_rate_to_clk()
177 struct samsung_usb2_phy_driver *drv = inst->drv; in exynos5250_isol()
181 switch (inst->cfg->id) { in exynos5250_isol()
194 regmap_update_bits(drv->reg_pmu, offset, mask, on ? 0 : mask); in exynos5250_isol()
[all …]
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| /kernel/linux/linux-6.6/drivers/phy/qualcomm/ |
| D | phy-qcom-usb-hsic.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/phy/phy.h>
10 #include <linux/pinctrl/pinctrl-state.h>
19 struct phy *phy; member
26 static int qcom_usb_hsic_phy_power_on(struct phy *phy) in qcom_usb_hsic_phy_power_on() argument
28 struct qcom_usb_hsic_phy *uphy = phy_get_drvdata(phy); in qcom_usb_hsic_phy_power_on()
29 struct ulpi *ulpi = uphy->ulpi; in qcom_usb_hsic_phy_power_on()
33 ret = clk_prepare_enable(uphy->phy_clk); in qcom_usb_hsic_phy_power_on()
37 ret = clk_prepare_enable(uphy->cal_clk); in qcom_usb_hsic_phy_power_on()
41 ret = clk_prepare_enable(uphy->cal_sleep_clk); in qcom_usb_hsic_phy_power_on()
[all …]
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| /kernel/linux/linux-5.10/drivers/phy/qualcomm/ |
| D | phy-qcom-usb-hsic.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/phy/phy.h>
10 #include <linux/pinctrl/pinctrl-state.h>
19 struct phy *phy; member
26 static int qcom_usb_hsic_phy_power_on(struct phy *phy) in qcom_usb_hsic_phy_power_on() argument
28 struct qcom_usb_hsic_phy *uphy = phy_get_drvdata(phy); in qcom_usb_hsic_phy_power_on()
29 struct ulpi *ulpi = uphy->ulpi; in qcom_usb_hsic_phy_power_on()
33 ret = clk_prepare_enable(uphy->phy_clk); in qcom_usb_hsic_phy_power_on()
37 ret = clk_prepare_enable(uphy->cal_clk); in qcom_usb_hsic_phy_power_on()
41 ret = clk_prepare_enable(uphy->cal_sleep_clk); in qcom_usb_hsic_phy_power_on()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/ |
| D | nvidia,tegra124-xusb.txt | 8 --------------------
9 - compatible: Must be:
10 - Tegra124: "nvidia,tegra124-xusb"
11 - Tegra132: "nvidia,tegra132-xusb", "nvidia,tegra124-xusb"
12 - Tegra210: "nvidia,tegra210-xusb"
13 - Tegra186: "nvidia,tegra186-xusb"
14 - reg: Must contain the base and length of the xHCI host registers, XUSB FPCI
16 - reg-names: Must contain the following entries:
17 - "hcd"
18 - "fpci"
[all …]
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