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/kernel/linux/linux-5.10/drivers/net/ethernet/intel/e1000e/
Dmac.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
7 * e1000e_get_bus_info_pcie - Get PCIe bus information
8 * @hw: pointer to the HW structure
14 s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw) in e1000e_get_bus_info_pcie() argument
16 struct e1000_mac_info *mac = &hw->mac; in e1000e_get_bus_info_pcie()
17 struct e1000_bus_info *bus = &hw->bus; in e1000e_get_bus_info_pcie()
18 struct e1000_adapter *adapter = hw->adapter; in e1000e_get_bus_info_pcie()
21 cap_offset = adapter->pdev->pcie_cap; in e1000e_get_bus_info_pcie()
23 bus->width = e1000_bus_width_unknown; in e1000e_get_bus_info_pcie()
[all …]
D82571.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
22 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
23 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
24 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
25 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
26 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
28 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
29 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
30 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
[all …]
Dphy.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
6 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
7 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
10 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
36 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
37 * @hw: pointer to the HW structure
43 s32 e1000e_check_reset_block_generic(struct e1000_hw *hw) in e1000e_check_reset_block_generic() argument
53 * e1000e_get_phy_id - Retrieve the PHY ID and revision
54 * @hw: pointer to the HW structure
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/intel/e1000e/
Dmac.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
7 * e1000e_get_bus_info_pcie - Get PCIe bus information
8 * @hw: pointer to the HW structure
14 s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw) in e1000e_get_bus_info_pcie() argument
16 struct e1000_mac_info *mac = &hw->mac; in e1000e_get_bus_info_pcie()
17 struct e1000_bus_info *bus = &hw->bus; in e1000e_get_bus_info_pcie()
18 struct e1000_adapter *adapter = hw->adapter; in e1000e_get_bus_info_pcie()
21 cap_offset = adapter->pdev->pcie_cap; in e1000e_get_bus_info_pcie()
23 bus->width = e1000_bus_width_unknown; in e1000e_get_bus_info_pcie()
[all …]
D82571.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
22 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
23 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
24 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
25 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
26 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
28 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
29 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
30 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
[all …]
Dphy.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
7 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
8 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
11 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
37 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
38 * @hw: pointer to the HW structure
44 s32 e1000e_check_reset_block_generic(struct e1000_hw *hw) in e1000e_check_reset_block_generic() argument
54 * e1000e_get_phy_id - Retrieve the PHY ID and revision
55 * @hw: pointer to the HW structure
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/intel/e1000/
De1000_hw.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
10 static s32 e1000_check_downshift(struct e1000_hw *hw);
11 static s32 e1000_check_polarity(struct e1000_hw *hw,
13 static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
14 static void e1000_clear_vfta(struct e1000_hw *hw);
15 static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
17 static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);
18 static s32 e1000_detect_gig_phy(struct e1000_hw *hw);
19 static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/intel/e1000/
De1000_hw.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
11 static s32 e1000_check_downshift(struct e1000_hw *hw);
12 static s32 e1000_check_polarity(struct e1000_hw *hw,
14 static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
15 static void e1000_clear_vfta(struct e1000_hw *hw);
16 static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
18 static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);
19 static s32 e1000_detect_gig_phy(struct e1000_hw *hw);
20 static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/intel/igc/
Digc_mac.c1 // SPDX-License-Identifier: GPL-2.0
11 * igc_disable_pcie_master - Disables PCI-express master access
12 * @hw: pointer to the HW structure
14 * Returns 0 (0) if successful, else returns -10
15 * (-IGC_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
18 * Disables PCI-Express master access and verifies there are no pending
21 s32 igc_disable_pcie_master(struct igc_hw *hw) in igc_disable_pcie_master() argument
25 u32 ctrl; in igc_disable_pcie_master() local
27 ctrl = rd32(IGC_CTRL); in igc_disable_pcie_master()
28 ctrl |= IGC_CTRL_GIO_MASTER_DISABLE; in igc_disable_pcie_master()
[all …]
Digc_phy.c1 // SPDX-License-Identifier: GPL-2.0
7 * igc_check_reset_block - Check if PHY reset is blocked
8 * @hw: pointer to the HW structure
14 s32 igc_check_reset_block(struct igc_hw *hw) in igc_check_reset_block() argument
25 * igc_get_phy_id - Retrieve the PHY ID and revision
26 * @hw: pointer to the HW structure
31 s32 igc_get_phy_id(struct igc_hw *hw) in igc_get_phy_id() argument
33 struct igc_phy_info *phy = &hw->phy; in igc_get_phy_id()
37 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); in igc_get_phy_id()
41 phy->id = (u32)(phy_id << 16); in igc_get_phy_id()
[all …]
Digc_base.c1 // SPDX-License-Identifier: GPL-2.0
13 * igc_reset_hw_base - Reset hardware
14 * @hw: pointer to the HW structure
19 static s32 igc_reset_hw_base(struct igc_hw *hw) in igc_reset_hw_base() argument
22 u32 ctrl; in igc_reset_hw_base() local
24 /* Prevent the PCI-E bus from sticking if there is no TLP connection in igc_reset_hw_base()
27 ret_val = igc_disable_pcie_master(hw); in igc_reset_hw_base()
29 hw_dbg("PCI-E Master disable polling has failed\n"); in igc_reset_hw_base()
40 ctrl = rd32(IGC_CTRL); in igc_reset_hw_base()
43 wr32(IGC_CTRL, ctrl | IGC_CTRL_DEV_RST); in igc_reset_hw_base()
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/intel/igc/
Digc_mac.c1 // SPDX-License-Identifier: GPL-2.0
11 * igc_disable_pcie_master - Disables PCI-express master access
12 * @hw: pointer to the HW structure
14 * Returns 0 (0) if successful, else returns -10
15 * (-IGC_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
18 * Disables PCI-Express master access and verifies there are no pending
21 s32 igc_disable_pcie_master(struct igc_hw *hw) in igc_disable_pcie_master() argument
25 u32 ctrl; in igc_disable_pcie_master() local
27 ctrl = rd32(IGC_CTRL); in igc_disable_pcie_master()
28 ctrl |= IGC_CTRL_GIO_MASTER_DISABLE; in igc_disable_pcie_master()
[all …]
Digc_phy.c1 // SPDX-License-Identifier: GPL-2.0
8 * igc_check_reset_block - Check if PHY reset is blocked
9 * @hw: pointer to the HW structure
15 s32 igc_check_reset_block(struct igc_hw *hw) in igc_check_reset_block() argument
26 * igc_get_phy_id - Retrieve the PHY ID and revision
27 * @hw: pointer to the HW structure
32 s32 igc_get_phy_id(struct igc_hw *hw) in igc_get_phy_id() argument
34 struct igc_phy_info *phy = &hw->phy; in igc_get_phy_id()
38 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); in igc_get_phy_id()
42 phy->id = (u32)(phy_id << 16); in igc_get_phy_id()
[all …]
Digc_base.c1 // SPDX-License-Identifier: GPL-2.0
13 * igc_reset_hw_base - Reset hardware
14 * @hw: pointer to the HW structure
19 static s32 igc_reset_hw_base(struct igc_hw *hw) in igc_reset_hw_base() argument
22 u32 ctrl; in igc_reset_hw_base() local
24 /* Prevent the PCI-E bus from sticking if there is no TLP connection in igc_reset_hw_base()
27 ret_val = igc_disable_pcie_master(hw); in igc_reset_hw_base()
29 hw_dbg("PCI-E Master disable polling has failed\n"); in igc_reset_hw_base()
40 ctrl = rd32(IGC_CTRL); in igc_reset_hw_base()
43 wr32(IGC_CTRL, ctrl | IGC_CTRL_RST); in igc_reset_hw_base()
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/serial/
Dst,stm32-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/st,stm32-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 - Erwan Le Ray <erwan.leray@foss.st.com>
15 - st,stm32-uart
16 - st,stm32f7-uart
17 - st,stm32h7-uart
34 st,hw-flow-ctrl:
35 description: enable hardware flow control (deprecated)
[all …]
Dst-asc.txt1 *st-asc(Serial Port)
4 - compatible : Should be "st,asc".
5 - reg, reg-names, interrupts, interrupt-names : Standard way to define device
7 Documentation/devicetree/bindings/resource-names.txt
10 - st,hw-flow-ctrl bool flag to enable hardware flow control.
11 - st,force-m1 bool flat to force asc to be in Mode-1 recommended
/kernel/linux/linux-5.10/drivers/net/ethernet/intel/igb/
De1000_mac.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
14 static s32 igb_set_default_fc(struct e1000_hw *hw);
15 static void igb_set_fc_watermarks(struct e1000_hw *hw);
18 * igb_get_bus_info_pcie - Get PCIe bus information
19 * @hw: pointer to the HW structure
25 s32 igb_get_bus_info_pcie(struct e1000_hw *hw) in igb_get_bus_info_pcie() argument
27 struct e1000_bus_info *bus = &hw->bus; in igb_get_bus_info_pcie()
32 bus->type = e1000_bus_type_pci_express; in igb_get_bus_info_pcie()
34 ret_val = igb_read_pcie_cap_reg(hw, in igb_get_bus_info_pcie()
[all …]
De1000_phy.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
10 static s32 igb_phy_setup_autoneg(struct e1000_hw *hw);
11 static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
13 static s32 igb_wait_autoneg(struct e1000_hw *hw);
14 static s32 igb_set_master_slave_mode(struct e1000_hw *hw);
31 * igb_check_reset_block - Check if PHY reset is blocked
32 * @hw: pointer to the HW structure
38 s32 igb_check_reset_block(struct e1000_hw *hw) in igb_check_reset_block() argument
48 * igb_get_phy_id - Retrieve the PHY ID and revision
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/intel/igb/
De1000_mac.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
14 static s32 igb_set_default_fc(struct e1000_hw *hw);
15 static void igb_set_fc_watermarks(struct e1000_hw *hw);
18 * igb_get_bus_info_pcie - Get PCIe bus information
19 * @hw: pointer to the HW structure
25 s32 igb_get_bus_info_pcie(struct e1000_hw *hw) in igb_get_bus_info_pcie() argument
27 struct e1000_bus_info *bus = &hw->bus; in igb_get_bus_info_pcie()
32 bus->type = e1000_bus_type_pci_express; in igb_get_bus_info_pcie()
34 ret_val = igb_read_pcie_cap_reg(hw, in igb_get_bus_info_pcie()
[all …]
De1000_phy.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
10 static s32 igb_phy_setup_autoneg(struct e1000_hw *hw);
11 static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
13 static s32 igb_wait_autoneg(struct e1000_hw *hw);
14 static s32 igb_set_master_slave_mode(struct e1000_hw *hw);
31 * igb_check_reset_block - Check if PHY reset is blocked
32 * @hw: pointer to the HW structure
38 s32 igb_check_reset_block(struct e1000_hw *hw) in igb_check_reset_block() argument
48 * igb_get_phy_id - Retrieve the PHY ID and revision
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/serial/
Dst,stm32-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/st,stm32-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 - Erwan Le Ray <erwan.leray@st.com>
13 - $ref: rs485.yaml
18 - st,stm32-uart
19 - st,stm32f7-uart
20 - st,stm32h7-uart
37 st,hw-flow-ctrl:
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/intel/ixgbe/
Dixgbe_82598.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
18 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
21 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
25 * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
26 * @hw: pointer to the HW structure
30 * than the 10ms recommended by the pci-e spec. To address this we need to
34 static void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw) in ixgbe_set_pcie_completion_timeout() argument
36 u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR); in ixgbe_set_pcie_completion_timeout()
39 if (ixgbe_removed(hw->hw_addr)) in ixgbe_set_pcie_completion_timeout()
[all …]
Dixgbe_82599.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
19 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
20 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
21 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
24 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
27 static void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw);
28 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
30 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
33 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/intel/ixgbe/
Dixgbe_82598.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
18 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
21 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
25 * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
26 * @hw: pointer to the HW structure
30 * than the 10ms recommended by the pci-e spec. To address this we need to
34 static void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw) in ixgbe_set_pcie_completion_timeout() argument
36 u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR); in ixgbe_set_pcie_completion_timeout()
39 if (ixgbe_removed(hw->hw_addr)) in ixgbe_set_pcie_completion_timeout()
[all …]
Dixgbe_82599.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
19 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
20 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
21 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
24 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
27 static void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw);
28 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
30 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
33 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
[all …]

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