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/kernel/linux/linux-6.6/arch/arm/boot/dts/nxp/imx/
Dimx7ulp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
8 #include <dt-bindings/clock/imx7ulp-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "imx7ulp-pinfunc.h"
15 interrupt-parent = <&intc>;
17 #address-cells = <1>;
18 #size-cells = <1>;
37 #address-cells = <1>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dimx7ulp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
8 #include <dt-bindings/clock/imx7ulp-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "imx7ulp-pinfunc.h"
15 interrupt-parent = <&intc>;
17 #address-cells = <1>;
18 #size-cells = <1>;
37 #address-cells = <1>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dimx7ulp-pcc-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx7ulp-pcc-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Clock bindings for Freescale i.MX7ULP Peripheral Clock Control (PCC) modules
10 - A.s. Dong <aisheng.dong@nxp.com>
13 i.MX7ULP Clock functions are under joint control of the System
14 Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
18 and A7 domain. Except for a few clock sources shared between two
19 domains, such as the System Oscillator clock, the Slow IRC (SIRC),
[all …]
Dimx7ulp-scg-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx7ulp-scg-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Clock bindings for Freescale i.MX7ULP System Clock Generation (SCG) modules
10 - A.s. Dong <aisheng.dong@nxp.com>
13 i.MX7ULP Clock functions are under joint control of the System
14 Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
18 and A7 domain. Except for a few clock sources shared between two
19 domains, such as the System Oscillator clock, the Slow IRC (SIRC),
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/
Dimx93.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx93-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/fsl,imx93-power.h>
11 #include <dt-bindings/thermal/thermal.h>
13 #include "imx93-pinfunc.h"
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
[all …]
Dimx8ulp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8ulp-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/power/imx8ulp-power.h>
10 #include <dt-bindings/thermal/thermal.h>
12 #include "imx8ulp-pinfunc.h"
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
[all …]
Dimx8qm-ss-dma.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
8 uart4_lpcg: clock-controller@5a4a0000 {
9 compatible = "fsl,imx8qxp-lpcg";
11 #clock-cells = <1>;
14 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
15 clock-output-names = "uart4_lpcg_baud_clk",
17 power-domains = <&pd IMX_SC_R_UART_4>;
20 can1_lpcg: clock-controller@5ace0000 {
21 compatible = "fsl,imx8qxp-lpcg";
[all …]
Dimx8dxl-ss-adma.dtsi1 // SPDX-License-Identifier: GPL-2.0+
7 clock-frequency = <160000000>;
11 clock-frequency = <160000000>;
19 compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
24 compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
29 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
34 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
39 compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart";
44 compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart";
49 compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart";
[all …]
Dimx8dxl-ss-conn.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 /delete-node/ &enet1_lpcg;
7 /delete-node/ &fec2;
10 conn_enet0_root_clk: clock-conn-enet0-root {
11 compatible = "fixed-clock";
12 #clock-cells = <0>;
13 clock-frequency = <250000000>;
14 clock-output-names = "conn_enet0_root_clk";
18 compatible = "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a";
20 interrupt-parent = <&gic>;
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dimx7ulp-pcc-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx7ulp-pcc-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX7ULP Peripheral Clock Control (PCC) modules Clock Controller
10 - A.s. Dong <aisheng.dong@nxp.com>
13 i.MX7ULP Clock functions are under joint control of the System
14 Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
18 and A7 domain. Except for a few clock sources shared between two
19 domains, such as the System Oscillator clock, the Slow IRC (SIRC),
[all …]
Dimx7ulp-scg-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx7ulp-scg-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX7ULP System Clock Generation (SCG) modules Clock Controller
10 - A.s. Dong <aisheng.dong@nxp.com>
13 i.MX7ULP Clock functions are under joint control of the System
14 Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
18 and A7 domain. Except for a few clock sources shared between two
19 domains, such as the System Oscillator clock, the Slow IRC (SIRC),
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/watchdog/
Dfsl-imx7ulp-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/fsl-imx7ulp-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Anson Huang <Anson.Huang@nxp.com>
13 - $ref: watchdog.yaml#
18 - const: fsl,imx7ulp-wdt
19 - items:
20 - const: fsl,imx8ulp-wdt
21 - const: fsl,imx7ulp-wdt
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/i2c/
Di2c-imx-lpi2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-imx-lpi2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Anson Huang <Anson.Huang@nxp.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
18 - enum:
19 - fsl,imx7ulp-lpi2c
20 - fsl,imx8qm-lpi2c
21 - items:
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/timer/
Dnxp,tpm-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/nxp,tpm-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
16 are clocked by an asynchronous clock that can remain enabled in low
23 - const: fsl,imx7ulp-tpm
24 - items:
25 - const: fsl,imx8ulp-tpm
26 - const: fsl,imx7ulp-tpm
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/i2c/
Di2c-imx-lpi2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-imx-lpi2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Anson Huang <Anson.Huang@nxp.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
18 - enum:
19 - fsl,imx7ulp-lpi2c
20 - items:
21 - enum:
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/spi/
Dspi-fsl-lpspi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-fsl-lpspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Anson Huang <Anson.Huang@nxp.com>
13 - $ref: /schemas/spi/spi-controller.yaml#
18 - enum:
19 - fsl,imx7ulp-spi
20 - fsl,imx8qxp-spi
21 - items:
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/
Dnxp,tpm-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/nxp,tpm-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
16 are clocked by an asynchronous clock that can remain enabled in low
22 const: fsl,imx7ulp-tpm
32 - description: SoC TPM ipg clock
33 - description: SoC TPM per clock
35 clock-names:
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/watchdog/
Dfsl-imx7ulp-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/fsl-imx7ulp-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Anson Huang <Anson.Huang@nxp.com>
13 - $ref: "watchdog.yaml#"
18 - fsl,imx7ulp-wdt
29 assigned-clocks:
32 assigned-clocks-parents:
35 timeout-sec: true
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/spi/
Dspi-fsl-lpspi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-fsl-lpspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Anson Huang <Anson.Huang@nxp.com>
13 - $ref: "/schemas/spi/spi-controller.yaml#"
18 - fsl,imx7ulp-spi
19 - fsl,imx8qxp-spi
29 - description: SoC SPI per clock
30 - description: SoC SPI ipg clock
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pwm/
Dimx-tpm-pwm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/imx-tpm-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Anson Huang <anson.huang@nxp.com>
17 "#pwm-cells":
22 - fsl,imx7ulp-pwm
27 assigned-clocks:
30 assigned-clock-parents:
37 - "#pwm-cells"
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pwm/
Dimx-tpm-pwm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/imx-tpm-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Anson Huang <anson.huang@nxp.com>
17 - $ref: pwm.yaml#
20 "#pwm-cells":
25 - fsl,imx7ulp-pwm
30 assigned-clocks:
33 assigned-clock-parents:
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/serial/
Dfsl-lpuart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/fsl-lpuart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fugang Duan <fugang.duan@nxp.com>
13 - $ref: rs485.yaml#
14 - $ref: serial.yaml#
19 - enum:
20 - fsl,vf610-lpuart
21 - fsl,ls1021a-lpuart
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/dma/
Dfsl,edma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 memory-mapped registers. channels are split into two groups, called
16 - Peng Fan <peng.fan@nxp.com>
21 - enum:
22 - fsl,vf610-edma
23 - fsl,imx7ulp-edma
24 - fsl,imx8qm-adma
25 - fsl,imx8qm-edma
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/
Dimx8qxp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
8 #include <dt-bindings/clock/imx8-clock.h>
9 #include <dt-bindings/firmware/imx/rsrc.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
14 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/serial/
Dfsl-lpuart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/fsl-lpuart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fugang Duan <fugang.duan@nxp.com>
13 - $ref: "rs485.yaml"
18 - enum:
19 - fsl,vf610-lpuart
20 - fsl,ls1021a-lpuart
21 - fsl,ls1028a-lpuart
[all …]

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