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Searched +full:imx8qxp +full:- +full:ldb (Results 1 – 10 of 10) sorted by relevance

/kernel/linux/linux-6.6/drivers/gpu/drm/bridge/imx/
DMakefile1 obj-$(CONFIG_DRM_IMX_LDB_HELPER) += imx-ldb-helper.o
2 obj-$(CONFIG_DRM_IMX8QM_LDB) += imx8qm-ldb.o
3 obj-$(CONFIG_DRM_IMX8QXP_LDB) += imx8qxp-ldb.o
4 obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o
5 obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o
6 obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI) += imx8qxp-pxl2dpi.o
Dimx8qxp-ldb.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/media-bus-format.h>
26 #include "imx-ldb-helper.h"
36 #define DRIVER_NAME "imx8qxp-ldb"
45 struct ldb base;
60 static inline struct imx8qxp_ldb *base_to_imx8qxp_ldb(struct ldb *base) in base_to_imx8qxp_ldb()
69 phy_cfg->bits_per_lane_and_dclk_cycle = 7; in imx8qxp_ldb_set_phy_cfg()
70 phy_cfg->lanes = 4; in imx8qxp_ldb_set_phy_cfg()
73 phy_cfg->differential_clk_rate = di_clk / 2; in imx8qxp_ldb_set_phy_cfg()
74 phy_cfg->is_slave = !imx8qxp_ldb->companion; in imx8qxp_ldb_set_phy_cfg()
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mfd/
Dfsl,imx8qxp-csr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/fsl,imx8qxp-csr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
17 use-case is for some other nodes to acquire a reference to the syscon node
18 by phandle, and the other typical use-case is that the operating system
23 pattern: "^syscon@[0-9a-f]+$"
27 - enum:
28 - fsl,imx8qxp-mipi-lvds-csr
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/bridge/
Dfsl,imx8qxp-ldb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-ldb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
13 The Freescale i.MX8qm/qxp LVDS Display Bridge(LDB) has two channels.
15 The i.MX8qm/qxp LDB is controlled by Control and Status Registers(CSR) module.
16 The CSR module, as a system controller, contains the LDB's configuration
19 For i.MX8qxp LDB, each channel supports up to 24bpp parallel input color
22 them to use. Two LDB channels from two LDB instances can work together in
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Dfsl,imx8qxp-pxl2dpi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pxl2dpi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
14 interfaces the pixel link 36-bit data output and the DSI controller’s
15 MIPI-DPI 24-bit data input, and inputs of LVDS Display Bridge(LDB) module
25 const: fsl,imx8qxp-pxl2dpi
27 fsl,sc-resource:
31 power-domains:
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/bus/
Dfsl,imx8qxp-pixel-link-msi-bus.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
18 i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks,
35 - $ref: simple-pm-bus.yaml#
37 # We need a select here so we don't match all nodes with 'simple-pm-bus'.
43 - fsl,imx8qxp-display-pixel-link-msi-bus
44 - fsl,imx8qm-display-pixel-link-msi-bus
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/kernel/linux/patches/linux-5.10/imx8mm_patch/patches/
D0001_linux_arch.patch7 Change-Id: I8c7b42f8858212fb4b2d56a871d3f4d5afc73954
9 diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
11 --- a/arch/arm64/Kconfig
13 @@ -183,7 +183,6 @@ config ARM64
17 - select HOLES_IN_ZONE
21 @@ -1023,6 +1022,9 @@ config NEED_PER_CPU_EMBED_FIRST_CHUNK
31 @@ -1148,7 +1150,7 @@ config XEN
35 - int
40 @@ -1182,15 +1184,6 @@ config UNMAP_KERNEL_AT_EL0
44 -config MITIGATE_SPECTRE_BRANCH_HISTORY
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D0005_linux_include.patch7 Change-Id: Icf23f02df7b566848af808b9eeaed889d1773e71
9 diff --git a/include/drm/bridge/cdns-mhdp.h b/include/drm/bridge/cdns-mhdp.h
12 --- /dev/null
13 +++ b/include/drm/bridge/cdns-mhdp.h
14 @@ -0,0 +1,921 @@
15 +/* SPDX-License-Identifier: GPL-2.0 */
18 + * Author: Chris Zhong <zyw@rock-chips.com>
39 +#include <sound/hdmi-codec.h>
489 +#define F_HDMI_ENCODING(x) (((x) & ((1 << 2) - 1)) << 16)
490 +#define F_VIF_DATA_WIDTH(x) (((x) & ((1 << 2) - 1)) << 2)
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/kernel/linux/linux-6.6/
DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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/kernel/linux/patches/linux-5.10/imx8mm_patch/patches/drivers/
D0020_linux_drivers_gpu.patch7 Change-Id: Ie95ebc16d7424b75135df39b9e20893d1a5171d6
9 diff --git a/drivers/gpu/Makefile b/drivers/gpu/Makefile
11 --- a/drivers/gpu/Makefile
13 @@ -3,6 +3,7 @@
16 obj-$(CONFIG_TEGRA_HOST1X) += host1x/
17 +obj-y += imx/
18 obj-y += drm/ vga/
19 obj-$(CONFIG_IMX_IPUV3_CORE) += ipu-v3/
20 obj-$(CONFIG_TRACE_GPU_MEM) += trace/
21 diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
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