| /kernel/linux/linux-6.6/drivers/clk/rockchip/ |
| D | clk-mmc-phase.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
41 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
58 raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift); in rockchip_mmc_get_phase()
82 u32 delay; in rockchip_mmc_set_phase() local
98 return -EINVAL; in rockchip_mmc_set_phase()
105 * Due to the inexact nature of the "fine" delay, we might in rockchip_mmc_set_phase()
106 * actually go non-monotonic. We don't go _too_ monotonic in rockchip_mmc_set_phase()
113 * On one extreme (if delay is actually 44ps): in rockchip_mmc_set_phase()
115 * The other (if delay is actually 77ps): in rockchip_mmc_set_phase()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/rockchip/ |
| D | clk-mmc-phase.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
41 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
58 raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift); in rockchip_mmc_get_phase()
82 u32 delay; in rockchip_mmc_set_phase() local
98 return -EINVAL; in rockchip_mmc_set_phase()
105 * Due to the inexact nature of the "fine" delay, we might in rockchip_mmc_set_phase()
106 * actually go non-monotonic. We don't go _too_ monotonic in rockchip_mmc_set_phase()
113 * On one extreme (if delay is actually 44ps): in rockchip_mmc_set_phase()
115 * The other (if delay is actually 77ps): in rockchip_mmc_set_phase()
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/mmp/ |
| D | clk-apbc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/delay.h>
27 unsigned int delay; member
42 if (apbc->lock) in clk_apbc_prepare()
43 spin_lock_irqsave(apbc->lock, flags); in clk_apbc_prepare()
45 data = readl_relaxed(apbc->base); in clk_apbc_prepare()
46 if (apbc->flags & APBC_POWER_CTRL) in clk_apbc_prepare()
49 writel_relaxed(data, apbc->base); in clk_apbc_prepare()
51 if (apbc->lock) in clk_apbc_prepare()
52 spin_unlock_irqrestore(apbc->lock, flags); in clk_apbc_prepare()
[all …]
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| D | clk-gate.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
13 #include <linux/delay.h>
31 if (gate->lock) in mmp_clk_gate_enable()
32 spin_lock_irqsave(gate->lock, flags); in mmp_clk_gate_enable()
34 tmp = readl(gate->reg); in mmp_clk_gate_enable()
35 tmp &= ~gate->mask; in mmp_clk_gate_enable()
36 tmp |= gate->val_enable; in mmp_clk_gate_enable()
37 writel(tmp, gate->reg); in mmp_clk_gate_enable()
39 if (gate->lock) in mmp_clk_gate_enable()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/mmp/ |
| D | clk-apbc.c | 15 #include <linux/delay.h>
30 unsigned int delay; member
45 if (apbc->lock) in clk_apbc_prepare()
46 spin_lock_irqsave(apbc->lock, flags); in clk_apbc_prepare()
48 data = readl_relaxed(apbc->base); in clk_apbc_prepare()
49 if (apbc->flags & APBC_POWER_CTRL) in clk_apbc_prepare()
52 writel_relaxed(data, apbc->base); in clk_apbc_prepare()
54 if (apbc->lock) in clk_apbc_prepare()
55 spin_unlock_irqrestore(apbc->lock, flags); in clk_apbc_prepare()
57 udelay(apbc->delay); in clk_apbc_prepare()
[all …]
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| D | clk-gate.c | 12 #include <linux/clk-provider.h>
16 #include <linux/delay.h>
34 if (gate->lock) in mmp_clk_gate_enable()
35 spin_lock_irqsave(gate->lock, flags); in mmp_clk_gate_enable()
37 tmp = readl(gate->reg); in mmp_clk_gate_enable()
38 tmp &= ~gate->mask; in mmp_clk_gate_enable()
39 tmp |= gate->val_enable; in mmp_clk_gate_enable()
40 writel(tmp, gate->reg); in mmp_clk_gate_enable()
42 if (gate->lock) in mmp_clk_gate_enable()
43 spin_unlock_irqrestore(gate->lock, flags); in mmp_clk_gate_enable()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/panel/ |
| D | samsung,s6e8aa0.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrzej Hajda <a.hajda@samsung.com>
13 - $ref: panel-common.yaml#
20 reset-gpios: true
21 display-timings: true
23 vdd3-supply:
26 vci-supply:
29 power-on-delay:
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/panel/ |
| D | samsung,s6e8aa0.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrzej Hajda <a.hajda@samsung.com>
13 - $ref: panel-common.yaml#
20 reset-gpios: true
21 display-timings: true
23 vdd3-supply:
26 vci-supply:
29 power-on-delay:
[all …]
|
| /kernel/linux/linux-6.6/tools/testing/selftests/netfilter/ |
| D | conntrack_sctp_collision.sh | 2 # SPDX-License-Identifier: GPL-2.0
6 # 14:35:47.655279 IP CLIENT_IP.PORT > SERVER_IP.PORT: sctp (1) [INIT] [init tag: 2017837359]
7 # 14:35:48.353250 IP SERVER_IP.PORT > CLIENT_IP.PORT: sctp (1) [INIT] [init tag: 1187206187]
8 # 14:35:48.353275 IP CLIENT_IP.PORT > SERVER_IP.PORT: sctp (1) [INIT ACK] [init tag: 2017837359]
11 # 14:35:48.855335 IP SERVER_IP.PORT > CLIENT_IP.PORT: sctp (1) [INIT ACK] [init tag: 164579970]
13 # TOPO: SERVER_NS (link0)<--->(link1) ROUTER_NS (link2)<--->(link3) CLIENT_NS
15 CLIENT_NS=$(mktemp -u client-XXXXXXXX)
19 SERVER_NS=$(mktemp -u server-XXXXXXXX)
23 ROUTER_NS=$(mktemp -u router-XXXXXXXX)
32 ip -n $SERVER_NS link add link0 type veth peer name link1 netns $ROUTER_NS
[all …]
|
| /kernel/linux/linux-6.6/drivers/net/ethernet/stmicro/stmmac/ |
| D | dwmac-meson8b.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
35 /* TX clock delay in ns = "8ns / 4 * tx_dly_val" (where 8ns are exactly one
57 * the automatically delay and skew automatically (internally).
60 /* An internal counter based on the "timing-adjustment" clock. The counter is
62 * delay (= the counter value) when to start sampling RXEN and RXD[3:0].
66 * large input delay, the bit for that signal (RXEN = bit 0, RXD[3] = bit 1,
67 * ...) can be configured to be 1 to compensate for a delay of about 1ns.
73 /* Defined for adding a delay to the input RX_CLK for better timing.
112 data = readl(dwmac->regs + reg); in meson8b_dwmac_mask_bits()
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/imx/ |
| D | clk-lpcg-scu.c | 1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/clk-provider.h>
9 #include <linux/delay.h>
16 #include "clk-scu.h"
25 * struct clk_lpcg_scu - Description of LPCG clock
46 /* e10858 -LPCG clock gating register synchronization errata */
54 * through the interconnect is longer than the minimum delay in lpcg_e10858_writel()
56 * Adding a readl will provide sufficient delay to prevent in lpcg_e10858_writel()
57 * back-to-back writes. in lpcg_e10858_writel()
77 reg = readl_relaxed(clk->reg); in clk_lpcg_scu_enable()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/sunxi/ |
| D | clk-mod0.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
15 #include "clk-factors.h"
18 * sun4i_a10_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
29 if (req->rate > req->parent_rate) in sun4i_a10_get_mod0_factors()
30 req->rate = req->parent_rate; in sun4i_a10_get_mod0_factors()
32 div = DIV_ROUND_UP(req->parent_rate, req->rate); in sun4i_a10_get_mod0_factors()
45 req->rate = (req->parent_rate >> calcp) / calcm; in sun4i_a10_get_mod0_factors()
46 req->m = calcm - 1; in sun4i_a10_get_mod0_factors()
47 req->p = calcp; in sun4i_a10_get_mod0_factors()
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/sunxi/ |
| D | clk-mod0.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
15 #include "clk-factors.h"
18 * sun4i_a10_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
29 if (req->rate > req->parent_rate) in sun4i_a10_get_mod0_factors()
30 req->rate = req->parent_rate; in sun4i_a10_get_mod0_factors()
32 div = DIV_ROUND_UP(req->parent_rate, req->rate); in sun4i_a10_get_mod0_factors()
45 req->rate = (req->parent_rate >> calcp) / calcm; in sun4i_a10_get_mod0_factors()
46 req->m = calcm - 1; in sun4i_a10_get_mod0_factors()
47 req->p = calcp; in sun4i_a10_get_mod0_factors()
[all …]
|
| /kernel/linux/linux-5.10/drivers/net/ethernet/stmicro/stmmac/ |
| D | dwmac-meson8b.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
35 /* TX clock delay in ns = "8ns / 4 * tx_dly_val" (where 8ns are exactly one
57 * the automatically delay and skew automatically (internally).
60 /* An internal counter based on the "timing-adjustment" clock. The counter is
62 * delay (= the counter value) when to start sampling RXEN and RXD[3:0].
66 * large input delay, the bit for that signal (RXEN = bit 0, RXD[3] = bit 1,
67 * ...) can be configured to be 1 to compensate for a delay of about 1ns.
101 data = readl(dwmac->regs + reg); in meson8b_dwmac_mask_bits()
105 writel(data, dwmac->regs + reg); in meson8b_dwmac_mask_bits()
[all …]
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| /kernel/linux/linux-5.10/arch/mips/boot/dts/cavium-octeon/ |
| D | octeon_3xxx.dts | 1 // SPDX-License-Identifier: GPL-2.0
6 * use. Because of this, it contains a super-set of the available
15 phy0: ethernet-phy@0 {
17 marvell,reg-init =
21 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
22 /* irq, blink-activity, blink-link */
23 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
27 phy1: ethernet-phy@1 {
29 marvell,reg-init =
33 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
[all …]
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| /kernel/linux/linux-6.6/arch/mips/boot/dts/cavium-octeon/ |
| D | octeon_3xxx.dts | 1 // SPDX-License-Identifier: GPL-2.0
6 * use. Because of this, it contains a super-set of the available
15 phy0: ethernet-phy@0 {
17 marvell,reg-init =
21 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
22 /* irq, blink-activity, blink-link */
23 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
27 phy1: ethernet-phy@1 {
29 marvell,reg-init =
33 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/ |
| D | clk-palmas.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (c) 2013-2014 Texas Instruments, Inc.
13 #include <linux/clk-provider.h>
30 int delay; member
57 ret = palmas_update_bits(cinfo->palmas, PALMAS_RESOURCE_BASE, in palmas_clks_prepare()
58 cinfo->clk_desc->control_reg, in palmas_clks_prepare()
59 cinfo->clk_desc->enable_mask, in palmas_clks_prepare()
60 cinfo->clk_desc->enable_mask); in palmas_clks_prepare()
62 dev_err(cinfo->dev, "Reg 0x%02x update failed, %d\n", in palmas_clks_prepare()
63 cinfo->clk_desc->control_reg, ret); in palmas_clks_prepare()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/ |
| D | clk-palmas.c | 5 * Copyright (c) 2013-2014 Texas Instruments, Inc.
21 #include <linux/clk-provider.h>
39 int delay; member
66 ret = palmas_update_bits(cinfo->palmas, PALMAS_RESOURCE_BASE, in palmas_clks_prepare()
67 cinfo->clk_desc->control_reg, in palmas_clks_prepare()
68 cinfo->clk_desc->enable_mask, in palmas_clks_prepare()
69 cinfo->clk_desc->enable_mask); in palmas_clks_prepare()
71 dev_err(cinfo->dev, "Reg 0x%02x update failed, %d\n", in palmas_clks_prepare()
72 cinfo->clk_desc->control_reg, ret); in palmas_clks_prepare()
73 else if (cinfo->clk_desc->delay) in palmas_clks_prepare()
[all …]
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| /kernel/linux/linux-5.10/arch/arm/mach-pxa/ |
| D | mp900.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-pxa/mp900.c
7 * Based on mach-pxa/gumstix.c
13 #include <linux/init.h>
19 #include <asm/mach-types.h>
25 static void isp116x_pfm_delay(struct device *dev, int delay) in isp116x_pfm_delay() argument
30 int cyc = delay / 10; in isp116x_pfm_delay()
43 .delay = isp116x_pfm_delay,
66 .id = -1,
70 .name = "isp116x-hcd",
[all …]
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| /kernel/linux/linux-6.6/drivers/media/test-drivers/vidtv/ |
| D | vidtv_tuner.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
20 * struct vidtv_tuner_config - Configuration used to init the tuner.
22 * @mock_power_up_delay_msec: Simulate a power-up delay.
23 * @mock_tune_delay_msec: Simulate a tune delay.
24 * @vidtv_valid_dvb_t_freqs: The valid DVB-T frequencies to simulate.
25 * @vidtv_valid_dvb_c_freqs: The valid DVB-C frequencies to simulate.
26 * @vidtv_valid_dvb_s_freqs: The valid DVB-S frequencies to simulate.
30 * The configuration used to init the tuner module, usually filled
|
| /kernel/linux/linux-5.10/drivers/media/test-drivers/vidtv/ |
| D | vidtv_tuner.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
20 * struct vidtv_tuner_config - Configuration used to init the tuner.
22 * @mock_power_up_delay_msec: Simulate a power-up delay.
23 * @mock_tune_delay_msec: Simulate a tune delay.
24 * @vidtv_valid_dvb_t_freqs: The valid DVB-T frequencies to simulate.
25 * @vidtv_valid_dvb_c_freqs: The valid DVB-C frequencies to simulate.
26 * @vidtv_valid_dvb_s_freqs: The valid DVB-S frequencies to simulate.
30 * The configuration used to init the tuner module, usually filled
|
| /kernel/linux/linux-5.10/drivers/clk/tegra/ |
| D | clk-periph-gate.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
9 #include <linux/delay.h>
20 readl_relaxed(gate->clk_base + (gate->regs->enb_reg))
22 writel_relaxed(val, gate->clk_base + (gate->regs->enb_set_reg))
24 writel_relaxed(val, gate->clk_base + (gate->regs->enb_clr_reg))
27 readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
29 writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
31 #define periph_clk_to_bit(gate) (1 << (gate->clk_num % 32))
44 if (!(gate->flags & TEGRA_PERIPH_NO_RESET)) in clk_periph_is_enabled()
[all …]
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| /kernel/linux/linux-5.10/drivers/media/i2c/ |
| D | bt819.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * bt819 - BT819A VideoStream Decoder (Rockwell Part)
12 * - moved over to linux>=2.4.x i2c protocol (9/9/2002)
21 #include <linux/delay.h>
25 #include <media/v4l2-device.h>
26 #include <media/v4l2-ctrls.h>
29 MODULE_DESCRIPTION("Brooktree-819 video decoder driver");
35 MODULE_PARM_DESC(debug, "Debug level (0-1)");
38 /* ----------------------------------------------------------------------- */
57 return &container_of(ctrl->handler, struct bt819, hdl)->sd; in to_sd()
[all …]
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| /kernel/linux/linux-6.6/drivers/media/i2c/ |
| D | bt819.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * bt819 - BT819A VideoStream Decoder (Rockwell Part)
12 * - moved over to linux>=2.4.x i2c protocol (9/9/2002)
21 #include <linux/delay.h>
25 #include <media/v4l2-device.h>
26 #include <media/v4l2-ctrls.h>
29 MODULE_DESCRIPTION("Brooktree-819 video decoder driver");
35 MODULE_PARM_DESC(debug, "Debug level (0-1)");
38 /* ----------------------------------------------------------------------- */
57 return &container_of(ctrl->handler, struct bt819, hdl)->sd; in to_sd()
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/actions/ |
| D | owl-pll.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
6 // Author: David Liu <liuwei@actions-semi.com>
14 #include "owl-common.h"
32 u8 delay; member
51 .delay = _delay, \
63 .hw.init = CLK_HW_INIT(_name, \
78 .hw.init = CLK_HW_INIT_NO_PARENT(_name, \
93 .hw.init = CLK_HW_INIT_NO_PARENT(_name, \
99 #define mul_mask(m) ((1 << ((m)->width)) - 1)
|