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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/crypto/
Dqcom,inline-crypto-engine.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/qcom,inline-crypto-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. (QTI) Inline Crypto Engine
10 - Bjorn Andersson <andersson@kernel.org>
15 - enum:
16 - qcom,sm8450-inline-crypto-engine
17 - qcom,sm8550-inline-crypto-engine
18 - const: qcom,inline-crypto-engine
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/kernel/linux/linux-6.6/drivers/crypto/marvell/cesa/
Dcesa.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <crypto/internal/hash.h>
6 #include <crypto/internal/skcipher.h>
8 #include <linux/dma-direction.h>
70 * in Errata 4.12. It looks like that it was part of an IRQ-controller in FPGA
124 * /-----------\ 0
126 * |-----------| 0x20
128 * |-----------| 0x40
130 * |-----------| 0x40 (inplace)
132 * |-----------| 0x80
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Dcesa.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Support for Marvell's Cryptographic Engine and Security Accelerator (CESA)
5 * driver supports the TDMA engine on platforms on which it is available.
7 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
15 #include <linux/dma-mapping.h>
32 /* Limit of the crypto queue before reaching the backlog */
38 mv_cesa_dequeue_req_locked(struct mv_cesa_engine *engine, in mv_cesa_dequeue_req_locked() argument
43 *backlog = crypto_get_backlog(&engine->queue); in mv_cesa_dequeue_req_locked()
44 req = crypto_dequeue_request(&engine->queue); in mv_cesa_dequeue_req_locked()
52 static void mv_cesa_rearm_engine(struct mv_cesa_engine *engine) in mv_cesa_rearm_engine() argument
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Dcipher.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
12 #include <crypto/aes.h>
13 #include <crypto/internal/des.h>
15 #include <linux/dma-mapping.h>
40 static inline void
44 mv_cesa_req_dma_iter_init(&iter->base, req->cryptlen); in mv_cesa_skcipher_req_iter_init()
45 mv_cesa_sg_dma_iter_init(&iter->src, req->src, DMA_TO_DEVICE); in mv_cesa_skcipher_req_iter_init()
46 mv_cesa_sg_dma_iter_init(&iter->dst, req->dst, DMA_FROM_DEVICE); in mv_cesa_skcipher_req_iter_init()
49 static inline bool
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/kernel/linux/linux-5.10/drivers/crypto/marvell/cesa/
Dcesa.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <crypto/internal/hash.h>
6 #include <crypto/internal/skcipher.h>
8 #include <linux/dma-direction.h>
70 * in Errata 4.12. It looks like that it was part of an IRQ-controller in FPGA
124 * /-----------\ 0
126 * |-----------| 0x20
128 * |-----------| 0x40
130 * |-----------| 0x40 (inplace)
132 * |-----------| 0x80
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Dcesa.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Support for Marvell's Cryptographic Engine and Security Accelerator (CESA)
5 * driver supports the TDMA engine on platforms on which it is available.
7 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
15 #include <linux/dma-mapping.h>
32 /* Limit of the crypto queue before reaching the backlog */
38 mv_cesa_dequeue_req_locked(struct mv_cesa_engine *engine, in mv_cesa_dequeue_req_locked() argument
43 *backlog = crypto_get_backlog(&engine->queue); in mv_cesa_dequeue_req_locked()
44 req = crypto_dequeue_request(&engine->queue); in mv_cesa_dequeue_req_locked()
52 static void mv_cesa_rearm_engine(struct mv_cesa_engine *engine) in mv_cesa_rearm_engine() argument
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Dcipher.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
12 #include <crypto/aes.h>
13 #include <crypto/internal/des.h>
15 #include <linux/dma-mapping.h>
40 static inline void
44 mv_cesa_req_dma_iter_init(&iter->base, req->cryptlen); in mv_cesa_skcipher_req_iter_init()
45 mv_cesa_sg_dma_iter_init(&iter->src, req->src, DMA_TO_DEVICE); in mv_cesa_skcipher_req_iter_init()
46 mv_cesa_sg_dma_iter_init(&iter->dst, req->dst, DMA_FROM_DEVICE); in mv_cesa_skcipher_req_iter_init()
49 static inline bool
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/kernel/linux/linux-6.6/drivers/soc/qcom/
Dice.c1 // SPDX-License-Identifier: GPL-2.0
3 * Qualcomm ICE (Inline Crypto Engine) support.
5 * Copyright (c) 2013-2019, The Linux Foundation. All rights reserved.
31 /* BIST ("built-in self-test") status flags */
38 #define qcom_ice_writel(engine, val, reg) \ argument
39 writel((val), (engine)->base + (reg))
41 #define qcom_ice_readl(engine, reg) \ argument
42 readl((engine)->base + (reg))
55 struct device *dev = ice->dev; in qcom_ice_check_supported()
67 dev_info(dev, "Found QC Inline Crypto Engine (ICE) v%d.%d.%d\n", in qcom_ice_check_supported()
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/kernel/linux/linux-6.6/drivers/crypto/caam/
Dintern.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright 2008-2011 Freescale Semiconductor, Inc.
14 #include <crypto/engine.h>
16 /* Currently comes from Kconfig param as a ^2 (driver-required) */
20 * Maximum size for crypto-engine software queue based on Job Ring
21 * size (JOBR_DEPTH) and a THRESHOLD (reserved for the non-crypto-API
22 * requests that are not passed through crypto-engine)
25 #define CRYPTO_ENGINE_MAX_QLEN (JOBR_DEPTH - THRESHOLD)
39 * Storage for tracking each in-process entry moving across a ring
60 /* Private sub-storage for a single JobR */
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/kernel/linux/linux-6.6/drivers/crypto/intel/keembay/
Dkeembay-ocs-ecc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Intel Keem Bay OCS ECC Crypto Driver.
5 * Copyright (C) 2019-2021 Intel Corporation
10 #include <crypto/ecc_curve.h>
11 #include <crypto/ecdh.h>
12 #include <crypto/engine.h>
13 #include <crypto/internal/ecc.h>
14 #include <crypto/internal/kpp.h>
15 #include <crypto/kpp.h>
16 #include <crypto/rng.h>
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Docs-aes.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Intel Keem Bay OCS AES Crypto Driver.
5 * Copyright (C) 2018-2020 Intel Corporation
11 #include <linux/dma-mapping.h>
35 * struct ocs_aes_dev - AES device context.
43 * @engine: Crypto engine for the device.
52 struct crypto_engine *engine; member
56 * struct ocs_dll_desc - Descriptor of an OCS DMA Linked List.
81 * ocs_aes_bypass_op() - Use OCS DMA to copy data.
88 static inline int ocs_aes_bypass_op(struct ocs_aes_dev *aes_dev, in ocs_aes_bypass_op()
/kernel/linux/linux-5.10/drivers/crypto/
Dpicoxcell_crypto.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2010-2011 Picochip Ltd., Jamie Iles
5 #include <crypto/internal/aead.h>
6 #include <crypto/aes.h>
7 #include <crypto/algapi.h>
8 #include <crypto/authenc.h>
9 #include <crypto/internal/des.h>
10 #include <crypto/md5.h>
11 #include <crypto/sha.h>
12 #include <crypto/internal/skcipher.h>
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/kernel/linux/linux-6.6/drivers/crypto/ccp/
Dccp-crypto.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * AMD Cryptographic Coprocessor (CCP) crypto API support
16 #include <crypto/algapi.h>
17 #include <crypto/aes.h>
18 #include <crypto/internal/aead.h>
19 #include <crypto/aead.h>
20 #include <crypto/ctr.h>
21 #include <crypto/hash.h>
22 #include <crypto/sha1.h>
23 #include <crypto/sha2.h>
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/kernel/linux/linux-5.10/drivers/crypto/ccp/
Dccp-crypto.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * AMD Cryptographic Coprocessor (CCP) crypto API support
16 #include <crypto/algapi.h>
17 #include <crypto/aes.h>
18 #include <crypto/internal/aead.h>
19 #include <crypto/aead.h>
20 #include <crypto/ctr.h>
21 #include <crypto/hash.h>
22 #include <crypto/sha.h>
23 #include <crypto/akcipher.h>
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/kernel/linux/linux-5.10/drivers/crypto/virtio/
Dvirtio_crypto_common.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* Common header for Virtio crypto device.
11 #include <linux/crypto.h>
14 #include <crypto/aead.h>
15 #include <crypto/aes.h>
16 #include <crypto/engine.h>
31 struct crypto_engine *engine; member
127 struct crypto_engine *engine, void *vreq);
132 static inline int virtio_crypto_get_current_node(void) in virtio_crypto_get_current_node()
/kernel/linux/linux-6.6/drivers/crypto/virtio/
Dvirtio_crypto_common.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* Common header for Virtio crypto device.
11 #include <linux/crypto.h>
14 #include <crypto/aead.h>
15 #include <crypto/aes.h>
16 #include <crypto/engine.h>
31 struct crypto_engine *engine; member
130 struct crypto_engine *engine, void *vreq);
135 static inline int virtio_crypto_get_current_node(void) in virtio_crypto_get_current_node()
/kernel/linux/linux-5.10/include/crypto/
Dpcrypt.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * pcrypt - Parallel crypto engine.
12 #include <linux/crypto.h>
22 static inline void *pcrypt_request_ctx(struct pcrypt_request *req) in pcrypt_request_ctx()
24 return req->__ctx; in pcrypt_request_ctx()
27 static inline
30 return &req->padata; in pcrypt_request_padata()
33 static inline
/kernel/linux/linux-6.6/include/crypto/
Dpcrypt.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * pcrypt - Parallel crypto engine.
13 #include <linux/crypto.h>
22 static inline void *pcrypt_request_ctx(struct pcrypt_request *req) in pcrypt_request_ctx()
24 return req->__ctx; in pcrypt_request_ctx()
27 static inline
30 return &req->padata; in pcrypt_request_padata()
33 static inline
/kernel/linux/linux-6.6/drivers/mmc/host/
Dcqhci-crypto.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * CQHCI crypto engine (inline encryption) support
20 * Returns the crypto bits that should be set in bits 64-127 of the
23 static inline u64 cqhci_crypto_prep_task_desc(struct mmc_request *mrq) in cqhci_crypto_prep_task_desc()
25 if (!mrq->crypto_ctx) in cqhci_crypto_prep_task_desc()
28 /* We set max_dun_bytes_supported=4, so all DUNs should be 32-bit. */ in cqhci_crypto_prep_task_desc()
29 WARN_ON_ONCE(mrq->crypto_ctx->bc_dun[0] > U32_MAX); in cqhci_crypto_prep_task_desc()
32 CQHCI_CRYPTO_KEYSLOT(mrq->crypto_key_slot) | in cqhci_crypto_prep_task_desc()
33 mrq->crypto_ctx->bc_dun[0]; in cqhci_crypto_prep_task_desc()
38 static inline int cqhci_crypto_init(struct cqhci_host *host) in cqhci_crypto_init()
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mmc/
Dsdhci-msm.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SDHCI controller (sdhci-msm)
10 - Bhupesh Sharma <bhupesh.sharma@linaro.org>
19 - enum:
20 - qcom,sdhci-msm-v4
22 - items:
23 - enum:
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/kernel/linux/linux-6.6/drivers/crypto/ccree/
Dcc_driver.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
5 * ARM CryptoCell Linux Crypto Driver
16 #include <linux/dma-mapping.h>
17 #include <crypto/algapi.h>
18 #include <crypto/internal/skcipher.h>
19 #include <crypto/aes.h>
20 #include <crypto/sha1.h>
21 #include <crypto/sha2.h>
22 #include <crypto/aead.h>
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/kernel/linux/linux-5.10/drivers/crypto/ccree/
Dcc_driver.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
5 * ARM CryptoCell Linux Crypto Driver
16 #include <linux/dma-mapping.h>
17 #include <crypto/algapi.h>
18 #include <crypto/internal/skcipher.h>
19 #include <crypto/aes.h>
20 #include <crypto/sha.h>
21 #include <crypto/aead.h>
22 #include <crypto/authenc.h>
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/kernel/linux/linux-6.6/drivers/crypto/marvell/octeontx2/
Dotx2_cpt_common.h1 /* SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/crypto.h>
42 /* Take mbox id from end of CPT mbox range in AF (range 0xA00 - 0xBFF) */
49 * Message request to config cpt lf for inline inbound ipsec.
50 * This message is only used between CPT PF <-> CPT VF
63 * Message request and response to get engine group number
79 * Message request and response to get kernel crypto limits
80 * This messages are only used between CPT PF <-> CPT VF
111 * engine type (SE, IE, AE).
125 static inline void otx2_cpt_write64(void __iomem *reg_base, u64 blk, u64 slot, in otx2_cpt_write64()
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/kernel/linux/linux-6.6/drivers/mmc/core/
Dcrypto.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * MMC crypto engine (inline encryption) support
8 #include <linux/blk-crypto.h>
12 #include "crypto.h"
18 if (host->caps2 & MMC_CAP2_CRYPTO) in mmc_crypto_set_initial_state()
19 blk_crypto_reprogram_all_keys(&host->crypto_profile); in mmc_crypto_set_initial_state()
24 if (host->caps2 & MMC_CAP2_CRYPTO) in mmc_crypto_setup_queue()
25 blk_crypto_register(&host->crypto_profile, q); in mmc_crypto_setup_queue()
32 struct mmc_request *mrq = &mqrq->brq.mrq; in mmc_crypto_prepare_req()
35 if (!req->crypt_ctx) in mmc_crypto_prepare_req()
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/kernel/linux/linux-5.10/drivers/scsi/ufs/
Dufs-qcom-ice.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Qualcomm ICE (Inline Crypto Engine) support.
5 * Copyright (c) 2014-2019, The Linux Foundation. All rights reserved.
12 #include "ufshcd-crypto.h"
13 #include "ufs-qcom.h"
54 /* BIST ("built-in self-test"?) status flags */
62 writel((val), (host)->ice_mmio + (reg))
64 readl((host)->ice_mmio + (reg))
68 struct device *dev = host->hba->dev; in qcom_ice_supported()
81 dev_info(dev, "Found QC Inline Crypto Engine (ICE) v%d.%d.%d\n", in qcom_ice_supported()
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