Searched full:input_reg (Results 1 – 25 of 74) sorted by relevance
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| /kernel/linux/linux-6.6/drivers/pinctrl/freescale/ |
| D | pinctrl-imx.c | 217 * The input_reg[i] here is actually some IOMUXC general in imx_pmx_set_one_pin_mmio()
220 val = readl(ipctl->base + pin_mmio->input_reg); in imx_pmx_set_one_pin_mmio()
223 writel(val, ipctl->base + pin_mmio->input_reg); in imx_pmx_set_one_pin_mmio()
224 } else if (pin_mmio->input_reg) { in imx_pmx_set_one_pin_mmio()
231 pin_mmio->input_reg); in imx_pmx_set_one_pin_mmio()
234 pin_mmio->input_reg); in imx_pmx_set_one_pin_mmio()
237 pin_mmio->input_reg, pin_mmio->input_val); in imx_pmx_set_one_pin_mmio()
450 * <mux_reg conf_reg input_reg mux_mode input_val>
452 * <mux_conf_reg input_reg mux_mode input_val>
490 pin_mmio->input_reg = be32_to_cpu(*list++); in imx_pinctrl_parse_pin_mmio()
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| D | pinctrl-imx.h | 24 * @input_reg: the select input register offset for this pin if any
31 u16 input_reg; member
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| /kernel/linux/linux-5.10/drivers/pinctrl/freescale/ |
| D | pinctrl-imx.c | 215 * The input_reg[i] here is actually some IOMUXC general in imx_pmx_set_one_pin_mmio()
218 val = readl(ipctl->base + pin_mmio->input_reg); in imx_pmx_set_one_pin_mmio()
221 writel(val, ipctl->base + pin_mmio->input_reg); in imx_pmx_set_one_pin_mmio()
222 } else if (pin_mmio->input_reg) { in imx_pmx_set_one_pin_mmio()
229 pin_mmio->input_reg); in imx_pmx_set_one_pin_mmio()
232 pin_mmio->input_reg); in imx_pmx_set_one_pin_mmio()
235 pin_mmio->input_reg, pin_mmio->input_val); in imx_pmx_set_one_pin_mmio()
505 * <mux_reg conf_reg input_reg mux_mode input_val>
507 * <mux_conf_reg input_reg mux_mode input_val>
545 pin_mmio->input_reg = be32_to_cpu(*list++); in imx_pinctrl_parse_pin_mmio()
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| D | pinctrl-imx.h | 25 * @input_reg: the select input register offset for this pin if any
32 u16 input_reg; member
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pinctrl/ |
| D | fsl,imx8ulp-pinctrl.yaml | 35 setting for one pin. The first 4 integers <mux_config_reg input_reg
46 "input_reg" indicates the offset of select input register.
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| D | fsl,imxrt1050.yaml | 36 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
49 "input_reg" indicates the offset of select input register.
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| D | fsl,imx93-pinctrl.yaml | 38 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
51 "input_reg" indicates the offset of select input register.
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| D | fsl,imxrt1170.yaml | 36 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
49 "input_reg" indicates the offset of select input register.
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| D | fsl,imx8m-pinctrl.yaml | 39 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
53 "input_reg" indicates the offset of select input register.
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| D | fsl,imx7d-pinctrl.yaml | 44 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
57 "input_reg" indicates the offset of select input register.
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| D | fsl,imx6sx-pinctrl.txt | 9 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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| D | fsl,imx6sll-pinctrl.txt | 9 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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| D | fsl,imx6ul-pinctrl.txt | 10 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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| D | fsl,imx7ulp-pinctrl.txt | 17 <mux_conf_reg input_reg mux_mode input_val> are specified
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/ |
| D | fsl,imx8mq-pinctrl.yaml | 35 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
48 "input_reg" indicates the offset of select input register.
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| D | fsl,imx8mp-pinctrl.yaml | 35 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
48 "input_reg" indicates the offset of select input register.
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| D | fsl,imx8mm-pinctrl.yaml | 35 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
48 "input_reg" indicates the offset of select input register.
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| D | fsl,imx8mn-pinctrl.yaml | 35 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
48 "input_reg" indicates the offset of select input register.
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| D | fsl,imx6sx-pinctrl.txt | 9 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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| D | fsl,imx6sll-pinctrl.txt | 9 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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| D | fsl,imx6ul-pinctrl.txt | 10 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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| D | fsl,imx7ulp-pinctrl.txt | 17 <mux_conf_reg input_reg mux_mode input_val> are specified
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| D | fsl,imx7d-pinctrl.txt | 32 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/nxp/imx/ |
| D | imx6ull-pinfunc-snvs.h | 11 * <mux_reg conf_reg input_reg mux_mode input_val>
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | imx6ull-pinfunc-snvs.h | 11 * <mux_reg conf_reg input_reg mux_mode input_val>
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