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/arkcompiler/runtime_core/libabckit/include/cpp/headers/
Ddynamic_isa.h7 * http://www.apache.org/licenses/LICENSE-2.0
19 #include "instruction.h"
70 …* @brief Creates instruction with opcode LOAD_STRING. This instruction loads the string `string` i…
71 * @return Instruction
74 Instruction CreateLoadString(std::string_view string) &&;
77 …* @brief Creates instruction with opcode SUB2. This instruction computes the binary operation `inp…
78 * stores the result in returned instruction.
79 * @return Instruction
80 * @param [ in ] acc - Inst containing right operand.
81 * @param [ in ] input0 - Inst containing left operand.
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Ddynamic_isa_impl.h7 * http://www.apache.org/licenses/LICENSE-2.0
29 // NOLINTBEGIN(performance-unnecessary-value-param)
32 inline core::Module DynamicIsa::GetModule(Instruction inst) && in GetModule()
35 AbckitCoreModule *mdl = conf->cDynapi_->iGetModule(inst.GetView()); in GetModule()
40 inline Instruction DynamicIsa::SetModule(Instruction inst, core::Module mdl) && in SetModule()
43 conf->cDynapi_->iSetModule(inst.GetView(), mdl.GetView()); in SetModule()
48 inline AbckitIsaApiDynamicConditionCode DynamicIsa::GetConditionCode(Instruction inst) && in GetConditionCode()
51 AbckitIsaApiDynamicConditionCode cc = conf->cDynapi_->iGetConditionCode(inst.GetView()); in GetConditionCode()
56 inline Instruction DynamicIsa::SetConditionCode(Instruction inst, AbckitIsaApiDynamicConditionCode … in SetConditionCode()
59 conf->cDynapi_->iSetConditionCode(inst.GetView(), cc); in SetConditionCode()
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Dinstruction.h7 * http://www.apache.org/licenses/LICENSE-2.0
29 * @brief Instruction
31 class Instruction final : public ViewInResource<AbckitInst *, const Graph *> {
33 // We restrict constructors in order to prevent C/C++ API mix-up by user.
41 /// @brief abckit::DefaultHash<Instruction>
42 friend class abckit::DefaultHash<Instruction>;
48 * @brief Construct a new empty Instruction object
50 Instruction() : ViewInResource(nullptr), conf_(nullptr) in Instruction() function
56 * @brief Construct a new Instruction object
59 Instruction(const Instruction &other) = default;
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Dinstruction_impl.h7 * http://www.apache.org/licenses/LICENSE-2.0
20 #include "instruction.h"
29 // NOLINTBEGIN(performance-unnecessary-value-param)
32 inline Instruction Instruction::InsertAfter(Instruction inst) const in InsertAfter()
35 conf->cGapi_->iInsertAfter(GetView(), inst.GetView()); in InsertAfter()
37 return Instruction(GetView(), GetApiConfig(), GetResource()); in InsertAfter()
40 inline Instruction Instruction::InsertBefore(Instruction inst) const in InsertBefore()
43 conf->cGapi_->iInsertBefore(GetView(), inst.GetView()); in InsertBefore()
45 return Instruction(GetView(), GetApiConfig(), GetResource()); in InsertBefore()
48 inline void Instruction::Remove() const in Remove()
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Dgraph.h2 * Copyright (c) 2024-2025 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
22 #include "instruction.h"
35 // We restrict constructors in order to prevent C/C++ API mix-up by user.
133 * @param [ in ] bbId - ID of basic block.
139 * @brief Returns parameter instruction under given `index` of a `graph`.
140 * @return Parameter instruction under given `index` of a `graph`.
141 * @param [ in ] index - Index of the parameter.
144 Instruction GetParameter(uint32_t index) const;
147 * @brief Returns number of instruction parameters under a `graph`.
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/arkcompiler/runtime_core/static_core/compiler/optimizer/ir_builder/
Dinst_templates.yaml1 # Copyright (c) 2021-2024 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
15 binop: |-
18 % raise "Wrong binop instruction" unless opc
20 …auto inst = graph_->CreateInst<%= opc %>(<%= get_type(inst.dtype) %>, GetPc(instruction->GetAddres…
21 <%=template('operands', inst, '')-%>
23 binop_z: |-
25 auto inst_save_state = CreateSaveState(Opcode::SaveState, GetPc(instruction->GetAddress()));
26 …auto inst_check = graph_->CreateInstZeroCheck(<%= get_type(inst.dtype) %>, GetPc(instruction->GetA…
28 if (graph_->IsBytecodeOptimizer()) {
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/arkcompiler/runtime_core/static_core/libllvmbackend/transforms/passes/
Dgep_propagation.h2 * Copyright (c) 2023-2024 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
27 class Instruction; variable
39 // NOLINTNEXTLINE(readability-identifier-naming)
43 …sing SelectorSplitMap = llvm::DenseMap<llvm::Instruction *, std::pair<llvm::Instruction *, llvm::I…
45 void AddToVector(llvm::Instruction *inst, llvm::SmallVector<llvm::Instruction *> *toExpand,
46 llvm::SmallVector<llvm::Instruction *> *selectors);
50 …void SplitGepSelectors(llvm::Function *function, llvm::SmallVector<llvm::Instruction *> *selectors,
51 llvm::DenseMap<llvm::Instruction *, llvm::Instruction *> *sgeps);
53 … std::pair<llvm::Value *, llvm::Value *> GenerateInput(llvm::Value *input, llvm::Instruction *inst,
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Dgep_propagation.cpp2 * Copyright (c) 2023-2024 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
27 #define DEBUG_TYPE "gep-propagation"
41 using llvm::Instruction;
47 /// Optimize no-op PHINodes and Selects in place.
48 // NOLINTNEXTLINE(fuchsia-statically-constructed-objects)
49 static llvm::cl::opt<bool> g_optimizeNoop("gprop-optimize", llvm::cl::Hidden, llvm::cl::init(true));
64 void GepPropagation::AddToVector(Instruction *inst, SmallVector<Instruction *> *toExpand, in AddToVector()
65 SmallVector<Instruction *> *selectors) in AddToVector()
67 switch (inst->getOpcode()) { in AddToVector()
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Daarch64_fixup_sdiv.cpp7 * http://www.apache.org/licenses/LICENSE-2.0
22 #define DEBUG_TYPE "aarch64-fixup-sdiv"
32 bool AArch64FixupSDiv::ReplaceSelect(llvm::Instruction *selectInst) in ReplaceSelect()
34 auto cmp = llvm::cast<llvm::Instruction>(selectInst->getOperand(0U)); in ReplaceSelect()
35 auto sub = selectInst->getOperand(1U); in ReplaceSelect()
36 auto sdiv = selectInst->getOperand(2U); in ReplaceSelect()
38 // sub instruction may be replaced with value in ReplaceSelect()
39 auto sdivInst = llvm::cast<llvm::Instruction>(sdiv); in ReplaceSelect()
41 selectInst->replaceAllUsesWith(sdivInst); in ReplaceSelect()
42 sdivInst->takeName(selectInst); in ReplaceSelect()
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/arkcompiler/runtime_core/compiler/optimizer/ir/
Dinstructions.yaml1 # Copyright (c) 2021-2022 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
16 Opcode of the instruction
19 Describes signature of the instruction. Properties of the operands are separated by '-' symbol.
26 …C++ base that represent this opcode. In far future if we managed to generate also instruction clas…
30 Properties of the instruction, such as: arithmetic, binop, throw, etc
33 Modes which the instruction can be used in
36 # Templates aim to reduce boilerplate in instruction description.
39 - equal_common_types
40 - float_src_eq_dst_size
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/arkcompiler/runtime_core/compiler/optimizer/ir_builder/
Dinst_templates.yaml1 # Copyright (c) 2021-2022 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
15 binop: |-
18 % raise "Wrong binop instruction" unless opc
20 …auto inst = graph_->CreateInst<%= opc %>(<%= get_type(inst.dtype) %>, GetPc(instruction->GetAddres…
21 <%=template('operands', inst, '')-%>
23 binop_z: |-
25 auto inst_save_state = CreateSaveState(Opcode::SaveState, GetPc(instruction->GetAddress()));
26 …auto inst_check = graph_->CreateInstZeroCheck(<%= get_type(inst.dtype) %>, GetPc(instruction->GetA…
28 if (graph_->IsBytecodeOptimizer()) {
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/arkcompiler/ets_frontend/testTs/instype/
Drecordthis-expected.txt2 (instruction order, type): (-2, 111), (-1, 106),
4 (instruction order, type): (-2, 111), (-1, 102),
6 (instruction order, type): (-2, 111), (-1, 103),
8 (instruction order, type): (-2, 111), (-1, 104),
10 (instruction order, type): (-2, 111), (-1, 105),
12 (instruction order, type): (-2, 111), (-1, 107), (16, 4),
14 (instruction order, type): (-2, 101), (-1, 108),
16 (instruction order, type): (-2, 111), (-1, 109),
18 (instruction order, type): (-2, 111), (-1, 110),
20 (instruction order, type): (-1, 112), (9, 1),
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Drecordimport-expected.txt2 (instruction order, type): (-1, 101),
4 (instruction order, type): (-2, 105),
6 (instruction order, type): (-1, 103),
8 (instruction order, type): (-1, 104),
10 (instruction order, type): (8, 101), (10, 1), (12, 103), (14, 104), (16, 1), (18, 1), (20, 1), (22,…
12 (instruction order, type): (5, 101), (8, 105), (19, 107), (22, 102), (25, 103), (31, 104), (37, 106…
/arkcompiler/runtime_core/libabckit/src/irbuilder_dynamic/templates/
Dinst_templates.yaml6 # http://www.apache.org/licenses/LICENSE-2.0
15 binop: |-
18 % raise "Wrong binop instruction" unless opc
20 …auto inst = graph_->CreateInst<%= opc %>(<%= get_type(inst.dtype) %>, GetPc(instruction->GetAddres…
21 <%=template('operands', inst, '')-%>
23 binop_z: |-
25 …auto instSaveState = CreateSaveState(compiler::Opcode::SaveState, GetPc(instruction->GetAddress())…
26 …auto instCheck = graph_->CreateInstZeroCheck(<%= get_type(inst.dtype) %>, GetPc(instruction->GetAd…
28 …instCheck->SetInput(0, FindOrCreate32BitConstant(instruction->GetImm<<%= inst.get_format %>, 0>())…
30 instCheck->SetInput(0, <%= inst.get_input_string(1) %>);
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/arkcompiler/runtime_core/libabckit/include/c/isa/
Disa_dynamic.h2 * Copyright (c) 2024-2025 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
16 // CC-OFFNXT(超大头文件[C++] Oversized Header File) huge header file
271 * @param [ in ] inst - Inst to be inspected.
282 * @param [ in ] inst - Inst to be modified.
283 * @param [ in ] md - Module to be set.
296 * @param [ in ] inst - Inst to be inspected.
306 * @param [ in ] inst - Inst to be modified.
307 * @param [ in ] cc - Condition code to be set.
318 * @param [ in ] inst - Inst to be inspected.
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/arkcompiler/runtime_core/panda_guard/obfuscate/
Dgraph_analyzer.h7 * http://www.apache.org/licenses/LICENSE-2.0
31 * Get Related Lda.Str instruction
34 * @param index reg index, -1 as using default value
36 static void GetLdaStr(const InstructionInfo &inIns, InstructionInfo &outIns, int index = -1);
39 * Get Related instruction of DefineMethod
47 * Get Related instruction of definepropertybyname
62 * @param inIns defineclasswithbuffer instruction
68 * get stmodulevar bind define instruction
70 * @param defineIns bind define instruction
75 * get stobjbyname bind define instruction
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/arkcompiler/runtime_core/static_core/plugins/ets/compiler/optimizer/ir_builder/
Dets_inst_templates.yaml1 # Copyright (c) 2021-2025 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
14 ets: |-
18 if (graph_->IsAbcKit()) {
19 BuildLdObjByName<true>(instruction, <%= get_type(inst.dtype) %>);
21 BuildLdObjByName<false>(instruction, <%= get_type(inst.dtype) %>);
24 if (graph_->IsAbcKit()) {
25 BuildStObjByName<true>(instruction, <%= get_type(inst.type(0)) %>);
27 BuildStObjByName<false>(instruction, <%= get_type(inst.type(0)) %>);
31 BuildCallByName<<%= is_range ? 'true' : 'false' %>>(instruction);
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/arkcompiler/runtime_core/compiler/docs/
Dir_builder.md18 - some instructions don't specify its type, f.e. `mov` instruction may produce int32 as well as flo…
20 - constant hasn't type as well and if one constant is used in integer and float operations, it must…
22 - if constant is `0` and it is used in instruction that expects object(f.e. `mov.obj`), we need to …
23 constant instruction `NullPtr` to handle this situation.
53 4. Get next bytecode instruction from the current basic block.
54 5. Build the Panda IR instruction from the bytecode instruction:
55 - create auxiliary instructions (SaveState, NullCheck, etc) if needed
56 - set inputs from the virtual register map
57 - if has destination, update virtual register definition in the vreg map
58 6. If instruction is a terminator, goto 1, else goto 4.
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/arkcompiler/runtime_core/static_core/compiler/docs/
Dir_builder.md18 - some instructions don't specify its type, f.e. `mov` instruction may produce int32 as well as flo…
20 - constant hasn't type as well and if one constant is used in integer and float operations, it must…
22 - if constant is `0` and it is used in instruction that expects object(f.e. `mov.obj`), we need to …
23 constant instruction `NullPtr` to handle this situation.
53 4. Get next bytecode instruction from the current basic block.
54 5. Build the Panda IR instruction from the bytecode instruction:
55 - create auxiliary instructions (SaveState, NullCheck, etc) if needed
56 - set inputs from the virtual register map
57 - if has destination, update virtual register definition in the vreg map
58 6. If instruction is a terminator, goto 1, else goto 4.
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/arkcompiler/runtime_core/docs/
Dir_format.md7 * Compiler overhead about 100000 native instructions per a bytecode instruction(standard for JIT co…
60 * Supporting side exits for de-optimizations and removing cold code.
65 ## Instruction set
76 …ble to do arm specific optimizations. For this, need to support ARMv8-M Instruction Set(only those…
80 IR contains high- and low-level instructions with a single interface.
81 In the first step, Panda bytecode is converted to high level instruction and architecturally indepe…
87 …f 'native' instructions(ARM) that are spent compiling a single 'guest' instruction(from Bytecode).…
90 In Ahead-Of-Time(AOT) mode the overhead is less critical for us, so we can do more optimizations.
91 In Just-In-Time(JIT) mode need to strictly control the overhead to get the overall performance incr…
104 …e Assignment) form(used in LLVM, WebKit, HHVM, CoreCLR, IonMonkey) and Sea-of-Nodes(Hotspot, V8 Tu…
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/arkcompiler/runtime_core/libabckit/include/c/
Dir_core.h2 * Copyright (c) 2024-2025 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
74 * @param [ in ] graph - Graph to read ISA type from.
82 * @param [ in ] graph - Graph to be inspected.
94 * @param [ in ] graph - Graph to be inspected.
102 * @param [ in ] graph - Graph to be inspected.
110 * @param [ in ] graph - Graph to be inspected.
117 * @return `false` if was early exited. Otherwise - `true`.
118 * @param [ in ] graph - Graph to be inspected.
119 …* @param [ in, out ] data - Pointer to the user-defined data that will be passed to the callback `…
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/arkcompiler/runtime_core/tests/cts-generator/cts-template/
Djnez.obj.yaml1 # Copyright (c) 2021-2022 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
15 - name: PandaAssembly
20 - file-name: "jnez.obj"
24 …Transfer execution to an instruction at offset bytes from the beginning of the current instruction
26 instruction address.
28 - x_none
30 - sig: jnez.obj imm:i32
35 - file-name: "invalid_offset"
38 - branch_target
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Djeqz.obj.yaml1 # Copyright (c) 2021-2022 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
15 - name: PandaAssembly
20 - file-name: "jeqz.obj"
24 …Transfer execution to an instruction at offset bytes from the beginning of the current instruction
26 instruction address.
28 - x_none
30 - sig: jeqz.obj imm:i32
35 - file-name: "invalid_offset"
38 - branch_target
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/arkcompiler/runtime_core/static_core/tests/cts-generator/cts-template/
Djnez.obj.yaml1 # Copyright (c) 2021-2024 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
16 - file-name: "jnez.obj"
20 …Transfer execution to an instruction at offset bytes from the beginning of the current instruction
22 instruction address.
24 - x_none
26 - sig: jnez.obj imm:i32
30 - file-name: "invalid_offset"
33 - branch_target
35 - sig: jnez.obj imm:i32
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Djeqz.obj.yaml1 # Copyright (c) 2021-2024 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
16 - file-name: "jeqz.obj"
20 …Transfer execution to an instruction at offset bytes from the beginning of the current instruction
22 instruction address.
24 - x_none
26 - sig: jeqz.obj imm:i32
30 - file-name: "invalid_offset"
33 - branch_target
35 - sig: jeqz.obj imm:i32
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