| /kernel/linux/linux-5.10/drivers/mailbox/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
6 on-chip processors through queued messages and interrupt driven
51 running on the Cortex-M3 rWTM secure processor of the Armada 37xx
77 This driver provides support for inter-processor communication
78 between CPU cores and MCU processor on Some Rockchip SOCs.
161 providing an interface for invoking the inter-process communication
162 signals from the application processor to other masters.
174 tristate "APM SoC X-Gene SLIMpro Mailbox Controller"
177 An implementation of the APM X-Gene Interprocessor Communication
178 Mailbox (IPCM) between the ARM 64-bit cores and SLIMpro controller.
[all …]
|
| /kernel/linux/linux-6.6/drivers/firmware/tegra/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
8 IVC (Inter-VM Communication) protocol is part of the IPC
9 (Inter Processor Communication) framework on Tegra. It maintains the
19 BPMP (Boot and Power Management Processor) is designed to off-loading
|
| /kernel/linux/linux-5.10/drivers/firmware/tegra/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
8 IVC (Inter-VM Communication) protocol is part of the IPC
9 (Inter Processor Communication) framework on Tegra. It maintains the
18 BPMP (Boot and Power Management Processor) is designed to off-loading
|
| /kernel/linux/linux-6.6/drivers/mailbox/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
6 on-chip processors through queued messages and interrupt driven
16 Apple SoCs have various co-processors required for certain
70 running on the Cortex-M3 rWTM secure processor of the Armada 37xx
96 This driver provides support for inter-processor communication
97 between CPU cores and MCU processor on Some Rockchip SOCs.
184 module will be called mailbox-mpfs.
193 providing an interface for invoking the inter-process communication
194 signals from the application processor to other masters.
206 tristate "APM SoC X-Gene SLIMpro Mailbox Controller"
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/amdzen4/ |
| D | data-fabric.json | 4 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 0.",
12 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 1.",
20 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 2.",
28 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 3.",
36 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 4.",
44 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 5.",
52 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 6.",
60 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 7.",
68 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 8.",
76 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 9.",
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/mailbox/ |
| D | qcom-ipcc.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mailbox/qcom-ipcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. Inter-Processor Communication Controller
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
13 The Inter-Processor Communication Controller (IPCC) is a centralized hardware
14 to route interrupts across various subsystems. It involves a three-level
16 entity on the Application Processor Subsystem (APSS) that wants to listen to
18 a case, the client would be Modem (client-id is 2) and the signal would be
[all …]
|
| D | mtk,adsp-mbox.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/mtk,adsp-mbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
13 The MTK ADSP mailbox Inter-Processor Communication (IPC) enables the SoC
15 The MTK ADSP mailbox IPC also provides the ability for one processor to
16 signal the other processor using interrupts.
21 - mediatek,mt8195-adsp-mbox
22 - mediatek,mt8186-adsp-mbox
[all …]
|
| D | xlnx,zynqmp-ipi-mailbox.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/xlnx,zynqmp-ipi-mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx IPI(Inter Processor Interrupt) mailbox controller
10 The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage
14 +-------------------------------------+
16 +-------------------------------------+
17 +--------------------------------------------------+
18 TF-A | |
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mailbox/ |
| D | qcom-ipcc.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mailbox/qcom-ipcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. Inter-Processor Communication Controller
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
13 The Inter-Processor Communication Controller (IPCC) is a centralized hardware
14 to route interrupts across various subsystems. It involves a three-level
16 entity on the Application Processor Subsystem (APSS) that wants to listen to
18 a case, the client would be Modem (client-id is 2) and the signal would be
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/powerpc/nintendo/ |
| D | wii.txt | 11 - model : Should be "nintendo,wii"
12 - compatible : Should be "nintendo,wii"
16 This node represents the multi-function "Hollywood" chip, which packages
21 - compatible : Should be "nintendo,hollywood"
25 Represents the interface between the graphics processor and a external
30 - compatible : should be "nintendo,hollywood-vi","nintendo,flipper-vi"
31 - reg : should contain the VI registers location and length
32 - interrupts : should contain the VI interrupt
34 1.b) The Processor Interface (PI) node
36 Represents the data and control interface between the main processor
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/ |
| D | sifive,clint.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
19 The clock frequency of CLINT is specified via "timebase-frequency" DT
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/powerpc/nintendo/ |
| D | wii.txt | 11 - model : Should be "nintendo,wii"
12 - compatible : Should be "nintendo,wii"
16 This node represents the multi-function "Hollywood" chip, which packages
21 - compatible : Should be "nintendo,hollywood"
25 Represents the interface between the graphics processor and a external
30 - compatible : should be "nintendo,hollywood-vi","nintendo,flipper-vi"
31 - reg : should contain the VI registers location and length
32 - interrupts : should contain the VI interrupt
34 1.b) The Processor Interface (PI) node
36 Represents the data and control interface between the main processor
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/timer/ |
| D | sifive,clint.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
19 The clock frequency of CLINT is specified via "timebase-frequency" DT
[all …]
|
| /kernel/linux/linux-6.6/Documentation/arch/loongarch/ |
| D | irq-chip-model.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 Currently, LoongArch based processors (e.g. Loongson-3A5000) can only work together
10 I/O Interrupt Controller), HTVECINTC (Hyper-Transport Vector Interrupt Controller),
11 PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
12 in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
14 CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package
15 controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e.,
22 In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
24 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go
27 +-----+ +---------+ +-------+
[all …]
|
| /kernel/linux/linux-5.10/drivers/media/pci/cx18/ |
| D | cx18-scb.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 #include "cx18-mailbox.h"
14 /* NOTE: All ACK interrupts are in the SW2 register. All non-ACK interrupts
65 between SCB_OFFSET and SCB_OFFSET+SCB_RESERVED_SIZE-1 inclusive */
80 /* Offset where to find the Inter-Processor Communication data */
96 /* These fields form Inter-Processor Communication data which is used
102 /* bit 0: 1/0 processor ready/not ready. Set other bits to 0. */
|
| /kernel/linux/linux-6.6/drivers/media/pci/cx18/ |
| D | cx18-scb.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 #include "cx18-mailbox.h"
14 /* NOTE: All ACK interrupts are in the SW2 register. All non-ACK interrupts
65 between SCB_OFFSET and SCB_OFFSET+SCB_RESERVED_SIZE-1 inclusive */
80 /* Offset where to find the Inter-Processor Communication data */
96 /* These fields form Inter-Processor Communication data which is used
102 /* bit 0: 1/0 processor ready/not ready. Set other bits to 0. */
|
| /kernel/linux/linux-5.10/arch/arc/kernel/ |
| D | smp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 * -- Added support for Inter Processor Interrupts
9 * -- Initial Write (Borrowed heavily from ARM)
26 #include <asm/processor.h>
55 return -EINVAL; in arc_get_cpu_map()
58 return -EINVAL; in arc_get_cpu_map()
65 * "possible-cpus" property in DeviceTree pretend all [0..NR_CPUS-1] exist.
71 if (arc_get_cpu_map("possible-cpus", &cpumask)) { in arc_init_cpu_possible()
72 pr_warn("Failed to get possible-cpus from dtb, pretending all %u cpus exist\n", in arc_init_cpu_possible()
[all …]
|
| /kernel/linux/linux-6.6/arch/arc/kernel/ |
| D | smp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 * -- Added support for Inter Processor Interrupts
9 * -- Initial Write (Borrowed heavily from ARM)
29 #include <asm/processor.h>
54 return -EINVAL; in arc_get_cpu_map()
57 return -EINVAL; in arc_get_cpu_map()
64 * "possible-cpus" property in DeviceTree pretend all [0..NR_CPUS-1] exist.
70 if (arc_get_cpu_map("possible-cpus", &cpumask)) { in arc_init_cpu_possible()
71 pr_warn("Failed to get possible-cpus from dtb, pretending all %u cpus exist\n", in arc_init_cpu_possible()
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/misc/ |
| D | qcom,fastrpc.txt | 3 The FastRPC implements an IPC (Inter-Processor Communication)
6 to offload tasks to the DSP and free up the application processor for
9 - compatible:
14 - label
20 - #address-cells
25 - #size-cells
33 - All Compute context banks MUST contain the following properties:
35 - compatible:
38 Definition: must be "qcom,fastrpc-compute-cb"
40 - reg
[all …]
|
| /kernel/linux/linux-6.6/Documentation/translations/zh_CN/arch/loongarch/ |
| D | irq-chip-model.rst | 1 .. SPDX-License-Identifier: GPL-2.0
3 .. include:: ../../disclaimer-zh_CN.rst
5 :Original: Documentation/arch/loongarch/irq-chip-model.rst
15 HTVECINTC（Hyper-Transport Vector Interrupt Controller）、PCH-PIC（LS7A芯片组的主中
16 断控制器）、PCH-LPC（LS7A芯片组的LPC中断控制器）和PCH-MSI（MSI中断控制器）。
19 全局中断控制器（每个芯片一个，所有核共享），而PCH-PIC/PCH-LPC/PCH-MSI是CPU外部的中
26 在这种模型里面，IPI（Inter-Processor Interrupt）和CPU本地时钟中断直接发送到CPUINTC，
27 CPU串口（UARTs）中断发送到LIOINTC，而其他所有设备的中断则分别发送到所连接的PCH-PIC/
28 PCH-LPC/PCH-MSI，然后被HTVECINTC统一收集，再发送到LIOINTC，最后到达CPUINTC::
30 +-----+ +---------+ +-------+
[all …]
|
| /kernel/linux/linux-5.10/arch/ia64/include/asm/ |
| D | hw_irq.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (C) 2001-2003 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
23 * 1,3-14 are reserved from firmware
25 * 16-255 (vectored external interrupts) are available
37 #define AUTO_ASSIGN -1
42 * Vectors 0x10-0x1f are used for low priority interrupts, e.g. CMCI.
45 #define IA64_CMCP_VECTOR 0x1d /* corrected machine-check polling vector */
47 #define IA64_CMC_VECTOR 0x1f /* corrected machine-check interrupt vector */
49 * Vectors 0x20-0x2f are reserved for legacy ISA IRQs.
[all …]
|
| /kernel/linux/linux-6.6/arch/ia64/include/asm/ |
| D | hw_irq.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (C) 2001-2003 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
23 * 1,3-14 are reserved from firmware
25 * 16-255 (vectored external interrupts) are available
37 #define AUTO_ASSIGN -1
42 * Vectors 0x10-0x1f are used for low priority interrupts, e.g. CMCI.
45 #define IA64_CMCP_VECTOR 0x1d /* corrected machine-check polling vector */
47 #define IA64_CMC_VECTOR 0x1f /* corrected machine-check interrupt vector */
49 * Vectors 0x20-0x2f are reserved for legacy ISA IRQs.
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/misc/ |
| D | qcom,fastrpc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 The FastRPC implements an IPC (Inter-Processor Communication)
16 to offload tasks to the DSP and free up the application processor for
25 - adsp
26 - mdsp
27 - sdsp
28 - cdsp
[all …]
|
| /kernel/linux/linux-6.6/drivers/media/platform/mediatek/vcodec/encoder/ |
| D | venc_vpu_if.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
13 * struct venc_vpu_inst - encoder VPU driver instance
23 * @id: the id of inter-processor interrupt
|
| /kernel/linux/linux-5.10/drivers/media/platform/mtk-vcodec/ |
| D | venc_vpu_if.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
14 * struct venc_vpu_inst - encoder VPU driver instance
24 * @id: the id of inter-processor interrupt
|