| /kernel/linux/linux-6.6/kernel/irq/ |
| D | cpuhotplug.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Generic cpu hotunplug interrupt migration code copied from the
12 #include <linux/interrupt.h>
20 /* For !GENERIC_IRQ_EFFECTIVE_AFF_MASK this looks at general affinity mask */
28 * The cpumask_empty() check is a workaround for interrupt chips, in irq_needs_fixup()
29 * which do not implement effective affinity, but the architecture has in irq_needs_fixup()
30 * enabled the config switch. Use the general affinity mask instead. in irq_needs_fixup()
46 pr_warn("Eff. affinity %*pbl of IRQ %u contains only offline CPUs after offlining CPU %u\n", in irq_needs_fixup()
47 cpumask_pr_args(m), d->irq, cpu); in irq_needs_fixup()
59 const struct cpumask *affinity; in migrate_one_irq() local
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| D | irqdesc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
4 * Copyright (C) 2005-2006, Thomas Gleixner, Russell King
6 * This file contains the interrupt descriptor management code. Detailed
7 * information is available in Documentation/core-api/genericirq.rst
13 #include <linux/interrupt.h>
22 * lockdep: we want to handle all irq_desc locks as a single lock-class:
56 if (!zalloc_cpumask_var_node(&desc->irq_common_data.affinity, in alloc_masks()
58 return -ENOMEM; in alloc_masks()
61 if (!zalloc_cpumask_var_node(&desc->irq_common_data.effective_affinity, in alloc_masks()
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| D | manage.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
4 * Copyright (C) 2005-2006 Thomas Gleixner
15 #include <linux/interrupt.h>
50 while (irqd_irq_inprogress(&desc->irq_data)) in __synchronize_hardirq()
53 /* Ok, that indicated we're done: double-check carefully. */ in __synchronize_hardirq()
54 raw_spin_lock_irqsave(&desc->lock, flags); in __synchronize_hardirq()
55 inprogress = irqd_irq_inprogress(&desc->irq_data); in __synchronize_hardirq()
70 raw_spin_unlock_irqrestore(&desc->lock, flags); in __synchronize_hardirq()
77 * synchronize_hardirq - wait for pending hard IRQ handlers (on other CPUs)
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| D | affinity.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2016-2017 Christoph Hellwig.
6 #include <linux/interrupt.h>
14 affd->nr_sets = 1; in default_calc_sets()
15 affd->set_size[0] = affvecs; in default_calc_sets()
19 * irq_create_affinity_masks - Create affinity masks for multiqueue spreading
21 * @affd: Description of the affinity requirements
32 * Determine the number of vectors which need interrupt affinities in irq_create_affinity_masks()
37 if (nvecs > affd->pre_vectors + affd->post_vectors) in irq_create_affinity_masks()
38 affvecs = nvecs - affd->pre_vectors - affd->post_vectors; in irq_create_affinity_masks()
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| /kernel/linux/linux-5.10/kernel/irq/ |
| D | cpuhotplug.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Generic cpu hotunplug interrupt migration code copied from the
12 #include <linux/interrupt.h>
20 /* For !GENERIC_IRQ_EFFECTIVE_AFF_MASK this looks at general affinity mask */
28 * The cpumask_empty() check is a workaround for interrupt chips, in irq_needs_fixup()
29 * which do not implement effective affinity, but the architecture has in irq_needs_fixup()
30 * enabled the config switch. Use the general affinity mask instead. in irq_needs_fixup()
46 pr_warn("Eff. affinity %*pbl of IRQ %u contains only offline CPUs after offlining CPU %u\n", in irq_needs_fixup()
47 cpumask_pr_args(m), d->irq, cpu); in irq_needs_fixup()
59 const struct cpumask *affinity; in migrate_one_irq() local
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| D | irqdesc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
4 * Copyright (C) 2005-2006, Thomas Gleixner, Russell King
6 * This file contains the interrupt descriptor management code. Detailed
7 * information is available in Documentation/core-api/genericirq.rst
13 #include <linux/interrupt.h>
15 #include <linux/radix-tree.h>
23 * lockdep: we want to handle all irq_desc locks as a single lock-class:
57 if (!zalloc_cpumask_var_node(&desc->irq_common_data.affinity, in alloc_masks()
59 return -ENOMEM; in alloc_masks()
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| D | msi.c | 1 // SPDX-License-Identifier: GPL-2.0
21 * alloc_msi_entry - Allocate an initialize msi_entry
24 * @affinity: Optional pointer to an affinity mask array size of @nvec
26 * If @affinity is not NULL then an affinity array[@nvec] is allocated
27 * and the affinity masks and flags from @affinity are copied.
30 const struct irq_affinity_desc *affinity) in alloc_msi_entry() argument
38 INIT_LIST_HEAD(&desc->list); in alloc_msi_entry()
39 desc->dev = dev; in alloc_msi_entry()
40 desc->nvec_used = nvec; in alloc_msi_entry()
41 if (affinity) { in alloc_msi_entry()
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| D | manage.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
4 * Copyright (C) 2005-2006 Thomas Gleixner
15 #include <linux/interrupt.h>
51 while (irqd_irq_inprogress(&desc->irq_data)) in __synchronize_hardirq()
54 /* Ok, that indicated we're done: double-check carefully. */ in __synchronize_hardirq()
55 raw_spin_lock_irqsave(&desc->lock, flags); in __synchronize_hardirq()
56 inprogress = irqd_irq_inprogress(&desc->irq_data); in __synchronize_hardirq()
71 raw_spin_unlock_irqrestore(&desc->lock, flags); in __synchronize_hardirq()
78 * synchronize_hardirq - wait for pending hard IRQ handlers (on other CPUs)
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/interrupt-controller/ |
| D | apple,aic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple Interrupt Controller
10 - Hector Martin <marcan@marcan.st>
13 The Apple Interrupt Controller is a simple interrupt controller present on
19 - Level-triggered hardware IRQs wired to SoC blocks
20 - Single mask bit per IRQ
21 - Per-IRQ affinity setting
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| D | apple,aic2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple Interrupt Controller 2
10 - Hector Martin <marcan@marcan.st>
13 The Apple Interrupt Controller 2 is a simple interrupt controller present on
18 - Level-triggered hardware IRQs wired to SoC blocks
19 - Single mask bit per IRQ
20 - Automatic masking on event delivery (auto-ack)
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| D | arm,gic-v3.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Generic Interrupt Controller, version 3
10 - Marc Zyngier <maz@kernel.org>
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
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| /kernel/linux/linux-5.10/include/linux/ |
| D | irq.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
10 * Thanks. --rmk
36 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
38 * IRQ_TYPE_NONE - default, unspecified type
39 * IRQ_TYPE_EDGE_RISING - rising edge triggered
40 * IRQ_TYPE_EDGE_FALLING - falling edge triggered
41 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered
42 * IRQ_TYPE_LEVEL_HIGH - high level triggered
43 * IRQ_TYPE_LEVEL_LOW - low level triggered
44 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits
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| D | interrupt.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* interrupt.h */
24 * linux/ioport.h to select the interrupt line behaviour. When
25 * requesting an interrupt without specifying a IRQF_TRIGGER, the
42 * IRQF_SHARED - allow sharing the irq among several devices
43 * IRQF_PROBE_SHARED - set by callers when they expect sharing mismatches to occur
44 * IRQF_TIMER - Flag to mark this interrupt as timer interrupt
45 * IRQF_PERCPU - Interrupt is per cpu
46 * IRQF_NOBALANCING - Flag to exclude this interrupt from irq balancing
47 * IRQF_IRQPOLL - Interrupt is used for polling (only the interrupt that is
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| /kernel/linux/linux-6.6/drivers/pci/msi/ |
| D | api.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCI MSI/MSI-X — Exported APIs for device drivers
5 * Copyright (C) 2003-2004 Intel
17 * pci_enable_msi() - Enable MSI interrupt mode on device
21 * allocate a single interrupt vector. On success, the allocated vector
22 * Linux IRQ will be saved at @dev->irq. The driver must invoke
40 * pci_disable_msi() - Disable MSI interrupt mode on device
43 * Legacy device driver API to disable MSI interrupt mode on device,
44 * free earlier allocated interrupt vectors, and restore INTx emulation.
45 * The PCI device Linux IRQ (@dev->irq) is restored to its default
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| /kernel/linux/linux-6.6/include/linux/ |
| D | irq.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
10 * Thanks. --rmk
36 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
38 * IRQ_TYPE_NONE - default, unspecified type
39 * IRQ_TYPE_EDGE_RISING - rising edge triggered
40 * IRQ_TYPE_EDGE_FALLING - falling edge triggered
41 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered
42 * IRQ_TYPE_LEVEL_HIGH - high level triggered
43 * IRQ_TYPE_LEVEL_LOW - low level triggered
44 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits
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| D | interrupt.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* interrupt.h */
25 * linux/ioport.h to select the interrupt line behaviour. When
26 * requesting an interrupt without specifying a IRQF_TRIGGER, the
43 * IRQF_SHARED - allow sharing the irq among several devices
44 * IRQF_PROBE_SHARED - set by callers when they expect sharing mismatches to occur
45 * IRQF_TIMER - Flag to mark this interrupt as timer interrupt
46 * IRQF_PERCPU - Interrupt is per cpu
47 * IRQF_NOBALANCING - Flag to exclude this interrupt from irq balancing
48 * IRQF_IRQPOLL - Interrupt is used for polling (only the interrupt that is
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| /kernel/linux/linux-6.6/drivers/infiniband/hw/hfi1/ |
| D | affinity.c | 1 // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause
3 * Copyright(c) 2015 - 2020 Intel Corporation.
8 #include <linux/interrupt.h>
12 #include "affinity.h"
35 cpumask_clear(&set->mask); in init_cpu_mask_set()
36 cpumask_clear(&set->used); in init_cpu_mask_set()
37 set->gen = 0; in init_cpu_mask_set()
43 if (cpumask_equal(&set->mask, &set->used)) { in _cpu_mask_set_gen_inc()
48 set->gen++; in _cpu_mask_set_gen_inc()
49 cpumask_clear(&set->used); in _cpu_mask_set_gen_inc()
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| /kernel/linux/linux-5.10/drivers/infiniband/hw/hfi1/ |
| D | affinity.c | 2 * Copyright(c) 2015 - 2020 Intel Corporation.
24 * - Redistributions of source code must retain the above copyright
26 * - Redistributions in binary form must reproduce the above copyright
30 * - Neither the name of Intel Corporation nor the names of its
50 #include <linux/interrupt.h>
54 #include "affinity.h"
77 cpumask_clear(&set->mask); in init_cpu_mask_set()
78 cpumask_clear(&set->used); in init_cpu_mask_set()
79 set->gen = 0; in init_cpu_mask_set()
85 if (cpumask_equal(&set->mask, &set->used)) { in _cpu_mask_set_gen_inc()
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| /kernel/linux/linux-5.10/drivers/iommu/ |
| D | hyperv-iommu.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Hyper-V stub IOMMU driver.
12 #include <linux/interrupt.h>
29 * According 82093AA IO-APIC spec , IO APIC has a 24-entry Interrupt
30 * Redirection Table. Hyper-V exposes one single IO-APIC and so define
41 struct irq_data *parent = data->parent_data; in hyperv_ir_set_affinity()
46 /* Return error If new irq affinity is out of ioapic_max_cpumask. */ in hyperv_ir_set_affinity()
48 return -EINVAL; in hyperv_ir_set_affinity()
50 ret = parent->chip->irq_set_affinity(parent, mask, force); in hyperv_ir_set_affinity()
54 entry = data->chip_data; in hyperv_ir_set_affinity()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | arm,gic-v3.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Generic Interrupt Controller, version 3
10 - Marc Zyngier <marc.zyngier@arm.com>
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
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| /kernel/linux/linux-5.10/drivers/perf/ |
| D | arm_pmu_platform.c | 1 // SPDX-License-Identifier: GPL-2.0
31 int ret = -ENODEV; in probe_current_pmu()
35 for (; info->init != NULL; info++) { in probe_current_pmu()
36 if ((cpuid & info->mask) != info->cpuid) in probe_current_pmu()
38 ret = info->init(pmu); in probe_current_pmu()
49 struct pmu_hw_events __percpu *hw_events = pmu->hw_events; in pmu_parse_percpu_irq()
51 ret = irq_get_percpu_devid_partition(irq, &pmu->supported_cpus); in pmu_parse_percpu_irq()
55 for_each_cpu(cpu, &pmu->supported_cpus) in pmu_parse_percpu_irq()
56 per_cpu(hw_events->irq, cpu) = irq; in pmu_parse_percpu_irq()
63 return !!of_find_property(node, "interrupt-affinity", NULL); in pmu_has_irq_affinity()
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| /kernel/linux/linux-6.6/drivers/perf/ |
| D | arm_pmu_platform.c | 1 // SPDX-License-Identifier: GPL-2.0
30 int ret = -ENODEV; in probe_current_pmu()
34 for (; info->init != NULL; info++) { in probe_current_pmu()
35 if ((cpuid & info->mask) != info->cpuid) in probe_current_pmu()
37 ret = info->init(pmu); in probe_current_pmu()
48 struct pmu_hw_events __percpu *hw_events = pmu->hw_events; in pmu_parse_percpu_irq()
50 ret = irq_get_percpu_devid_partition(irq, &pmu->supported_cpus); in pmu_parse_percpu_irq()
54 for_each_cpu(cpu, &pmu->supported_cpus) in pmu_parse_percpu_irq()
55 per_cpu(hw_events->irq, cpu) = irq; in pmu_parse_percpu_irq()
62 return !!of_find_property(node, "interrupt-affinity", NULL); in pmu_has_irq_affinity()
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| /kernel/linux/linux-6.6/Documentation/arch/ia64/ |
| D | irq-redir.rst | 2 IRQ affinity on IA64 platforms
8 By writing to /proc/irq/IRQ#/smp_affinity the interrupt routing can be
10 that described in Documentation/core-api/irq/irq-affinity.rst for i386 systems.
14 CPUs. Only the first non-zero bit is taken into account.
21 first non-zero bit is the selected CPU. This format has been kept for
24 Set the delivery mode of interrupt 41 to fixed and route the
38 gives the target CPU mask for the specified interrupt vector. If the CPU
39 mask is preceded by the character "r", the interrupt is redirectable
49 IO-SAPIC interrupts are initialized with CPU#0 as their default target
55 - minimal for an idle task,
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| /kernel/linux/linux-5.10/Documentation/ia64/ |
| D | irq-redir.rst | 2 IRQ affinity on IA64 platforms
8 By writing to /proc/irq/IRQ#/smp_affinity the interrupt routing can be
10 that described in Documentation/core-api/irq/irq-affinity.rst for i386 systems.
14 CPUs. Only the first non-zero bit is taken into account.
21 first non-zero bit is the selected CPU. This format has been kept for
24 Set the delivery mode of interrupt 41 to fixed and route the
38 gives the target CPU mask for the specified interrupt vector. If the CPU
39 mask is preceded by the character "r", the interrupt is redirectable
49 IO-SAPIC interrupts are initialized with CPU#0 as their default target
55 - minimal for an idle task,
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| /kernel/linux/linux-5.10/block/ |
| D | blk-mq-rdma.c | 1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/blk-mq.h>
6 #include <linux/blk-mq-rdma.h>
10 * blk_mq_rdma_map_queues - provide a default queue mapping for rdma device
13 * @first_vec: first interrupt vectors to use for queues (usually 0)
16 * interrupt vetors as @set has queues. It will then query it's affinity mask
17 * and built queue mapping that maps a queue to the CPUs that have irq affinity
21 * @set->nr_hw_queues, or @dev does not provide an affinity mask for a
30 for (queue = 0; queue < map->nr_queues; queue++) { in blk_mq_rdma_map_queues()
36 map->mq_map[cpu] = map->queue_offset + queue; in blk_mq_rdma_map_queues()
|