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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/counter/
Dinterrupt-counter.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/counter/interrupt-counter.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Interrupt counter
10 - Oleksij Rempel <o.rempel@pengutronix.de>
13 A generic interrupt counter to measure interrupt frequency. It was developed
17 Interrupts or gpios are required. If both are defined, the interrupt will
22 const: interrupt-counter
31 - compatible
[all …]
/kernel/linux/linux-5.10/drivers/staging/comedi/drivers/
Damplc_dio200.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Copyright (C) 2005-2013 MEV Ltd. <https://www.mev.co.uk/>
9 * COMEDI - Linux Control and Measurement Device Interface
24 * [0] - I/O port base address
25 * [1] - IRQ (optional, but commands won't work without it)
32 * ------------- ------------- -------------
34 * 0 PPI-X PPI-X PPI-X
35 * 1 CTR-Y1 PPI-Y PPI-Y
36 * 2 CTR-Y2 CTR-Z1* CTR-Z1
37 * 3 CTR-Z1 INTERRUPT* CTR-Z2
[all …]
Damplc_dio200_pci.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (C) 2005-2013 MEV Ltd. <https://www.mev.co.uk/>
8 * COMEDI - Linux Control and Measurement Device Interface
30 * ------------- ------------- -------------
32 * 0 PPI-X PPI-X PPI-X
33 * 1 PPI-Y UNUSED UNUSED
34 * 2 CTR-Z1 PPI-Y UNUSED
35 * 3 CTR-Z2 UNUSED UNUSED
36 * 4 INTERRUPT CTR-Z1 CTR-Z1
37 * 5 CTR-Z2 CTR-Z2
[all …]
/kernel/linux/linux-6.6/drivers/comedi/drivers/
Damplc_dio200.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Copyright (C) 2005-2013 MEV Ltd. <https://www.mev.co.uk/>
9 * COMEDI - Linux Control and Measurement Device Interface
24 * [0] - I/O port base address
25 * [1] - IRQ (optional, but commands won't work without it)
32 * ------------- ------------- -------------
34 * 0 PPI-X PPI-X PPI-X
35 * 1 CTR-Y1 PPI-Y PPI-Y
36 * 2 CTR-Y2 CTR-Z1* CTR-Z1
37 * 3 CTR-Z1 INTERRUPT* CTR-Z2
[all …]
Damplc_dio200_pci.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (C) 2005-2013 MEV Ltd. <https://www.mev.co.uk/>
8 * COMEDI - Linux Control and Measurement Device Interface
30 * ------------- ------------- -------------
32 * 0 PPI-X PPI-X PPI-X
33 * 1 PPI-Y UNUSED UNUSED
34 * 2 CTR-Z1 PPI-Y UNUSED
35 * 3 CTR-Z2 UNUSED UNUSED
36 * 4 INTERRUPT CTR-Z1 CTR-Z1
37 * 5 CTR-Z2 CTR-Z2
[all …]
/kernel/linux/linux-6.6/drivers/counter/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Counter devices
8 select COUNTER
21 menuconfig COUNTER config
22 tristate "Counter support"
24 This enables counter device support through the Generic Counter
26 one or more of the counter device drivers below.
28 if COUNTER
31 tristate "ACCES 104-QUAD-8 driver"
37 Say yes here to build support for the ACCES 104-QUAD-8 quadrature
[all …]
Dinterrupt-cnt.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/counter.h>
9 #include <linux/interrupt.h>
17 #define INTERRUPT_CNT_NAME "interrupt-cnt"
32 struct counter_device *counter = dev_id; in interrupt_cnt_isr() local
33 struct interrupt_cnt_priv *priv = counter_priv(counter); in interrupt_cnt_isr()
35 atomic_inc(&priv->count); in interrupt_cnt_isr()
37 counter_push_event(counter, COUNTER_EVENT_CHANGE_OF_STATE, 0); in interrupt_cnt_isr()
42 static int interrupt_cnt_enable_read(struct counter_device *counter, in interrupt_cnt_enable_read() argument
45 struct interrupt_cnt_priv *priv = counter_priv(counter); in interrupt_cnt_enable_read()
[all …]
/kernel/linux/linux-5.10/drivers/net/wan/
Dhd64572.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * hd64572.h Description of the Hitachi HD64572 (SCA-II), valid for
8 * Copyright: (c) 2000-2001 Cyclades Corp.
15 * PC300 initial CVS version (3.4.0-pre1)
36 /* Interrupt Registers */
37 #define IVR 0x60 /* Interrupt Vector Register */
38 #define IMVR 0x64 /* Interrupt Modified Vector Register */
39 #define ITCR 0x68 /* Interrupt Control Register */
40 #define ISR0 0x6c /* Interrupt Status Register 0 */
41 #define ISR1 0x70 /* Interrupt Status Register 1 */
[all …]
/kernel/linux/linux-6.6/drivers/net/wan/
Dhd64572.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * hd64572.h Description of the Hitachi HD64572 (SCA-II), valid for
8 * Copyright: (c) 2000-2001 Cyclades Corp.
15 * PC300 initial CVS version (3.4.0-pre1)
36 /* Interrupt Registers */
37 #define IVR 0x60 /* Interrupt Vector Register */
38 #define IMVR 0x64 /* Interrupt Modified Vector Register */
39 #define ITCR 0x68 /* Interrupt Control Register */
40 #define ISR0 0x6c /* Interrupt Status Register 0 */
41 #define ISR1 0x70 /* Interrupt Status Register 1 */
[all …]
/kernel/linux/linux-5.10/Documentation/riscv/
Dpmu.rst2 Supporting PMUs on RISC-V platforms
8 ------------
10 As of this writing, perf_event-related features mentioned in The RISC-V ISA
23 Counters are just free-running all the time in our case.
24 * Interrupt caused by counter overflow
26 * Interrupt indicator
27 It is not possible to have many interrupt ports for all counters, so an
28 interrupt indicator is required for software to tell which counter has
33 hardware-extension for M-S-U model machines to write counters directly.
44 -----------------
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/kernel/linux/linux-6.6/arch/arm/kernel/
Dperf_event_v6.c1 // SPDX-License-Identifier: GPL-2.0
3 * ARMv6 Performance counter handling code.
7 * ARMv6 has 2 configurable performance counters and a single cycle counter.
16 * the event bus. The procedure for disabling a configurable counter is:
17 * - change the counter to count the ETMEXTOUT[0] signal (0x20). This
18 * effectively stops the counter from counting.
19 * - disable the counter's interrupt generation (each counter has it's
20 * own interrupt enable bit).
21 * Once stopped, the counter value can be written as 0 to reset.
23 * To enable a counter:
[all …]
/kernel/linux/linux-5.10/arch/arm/kernel/
Dperf_event_v6.c1 // SPDX-License-Identifier: GPL-2.0
3 * ARMv6 Performance counter handling code.
7 * ARMv6 has 2 configurable performance counters and a single cycle counter.
16 * the event bus. The procedure for disabling a configurable counter is:
17 * - change the counter to count the ETMEXTOUT[0] signal (0x20). This
18 * effectively stops the counter from counting.
19 * - disable the counter's interrupt generation (each counter has it's
20 * own interrupt enable bit).
21 * Once stopped, the counter value can be written as 0 to reset.
23 * To enable a counter:
[all …]
/kernel/liteos_a/arch/arm/arm/src/pmu/
Darmv7_pmu.c2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
71 UINT32 counter = ARMV7_IDX2CNT(index); in Armv7PmuSelCnt() local
72 __asm__ volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (counter)); in Armv7PmuSelCnt()
79 PRINT_ERR("CPU writing wrong counter %u\n", index); in Armv7PmuSetCntPeriod()
90 PRINT_DEBUG("bind event: %u to counter: %u\n", value, index); in Armv7BindEvt2Cnt()
98 UINT32 counter = ARMV7_IDX2CNT(index); in Armv7EnableCnt() local
99 PRINT_DEBUG("index : %u, counter: %u\n", index, counter); in Armv7EnableCnt()
100 __asm__ volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (ARMV7_CNT2BIT(counter))); in Armv7EnableCnt()
105 UINT32 counter = ARMV7_IDX2CNT(index); in Armv7DisableCnt() local
[all …]
/kernel/linux/linux-6.6/arch/mips/kernel/
Dcevt-r4k.c7 * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
10 #include <linux/interrupt.h>
17 #include <asm/cevt-r4k.h>
28 res = ((int)(read_c0_count() - cnt) >= 0) ? -ETIME : 0; in mips_next_event()
33 * calculate_min_delta() - Calculate a good minimum delta for mips_next_event().
67 cnt = read_c0_count() - cnt; in calculate_min_delta()
73 j, ARRAY_SIZE(buf1) - 1); in calculate_min_delta()
74 for (; l > k; --l) in calculate_min_delta()
75 buf1[l] = buf1[l - 1]; in calculate_min_delta()
85 if (buf1[ARRAY_SIZE(buf1) - 1] < buf2[k]) { in calculate_min_delta()
[all …]
/kernel/linux/linux-5.10/arch/mips/kernel/
Dcevt-r4k.c7 * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
10 #include <linux/interrupt.h>
17 #include <asm/cevt-r4k.h>
28 res = ((int)(read_c0_count() - cnt) >= 0) ? -ETIME : 0; in mips_next_event()
33 * calculate_min_delta() - Calculate a good minimum delta for mips_next_event().
67 cnt = read_c0_count() - cnt; in calculate_min_delta()
73 j, ARRAY_SIZE(buf1) - 1); in calculate_min_delta()
74 for (; l > k; --l) in calculate_min_delta()
75 buf1[l] = buf1[l - 1]; in calculate_min_delta()
85 if (buf1[ARRAY_SIZE(buf1) - 1] < buf2[k]) { in calculate_min_delta()
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/freescale/
Dgianfar.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
13 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
16 * -Add support for module parameters
17 * -Add patch for ethtool phys id
27 #include <linux/interrupt.h>
70 #define DRV_NAME "gfar-enet"
95 #define GFAR_RXB_SIZE rounddown(GFAR_RXB_TRUESIZE - GFAR_SKBFRAG_OVR, 64)
98 #define TX_RING_MOD_MASK(size) (size-1)
99 #define RX_RING_MOD_MASK(size) (size-1)
111 * time described by a value of 1 in the interrupt
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/sun/
Dsunbmac.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define GLOB_MSIZE 0x0cUL /* Local-mem size (64K) */
44 #define CREG_RIMASK 0x10UL /* RX Interrupt Mask */
45 #define CREG_TIMASK 0x14UL /* TX Interrupt Mask */
46 #define CREG_QMASK 0x18UL /* QEC Error Interrupt Mask */
47 #define CREG_BMASK 0x1cUL /* BigMAC Error Interrupt Mask*/
52 #define CREG_CCNT 0x30UL /* Collision Counter */
58 #define CREG_STAT_TXIRQ 0x00200000 /* Transmit Interrupt */
63 #define CREG_STAT_RXIRQ 0x00000020 /* Receive Interrupt */
87 /* 0x004-->0x0fc, reserved */
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/sun/
Dsunbmac.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define GLOB_MSIZE 0x0cUL /* Local-mem size (64K) */
44 #define CREG_RIMASK 0x10UL /* RX Interrupt Mask */
45 #define CREG_TIMASK 0x14UL /* TX Interrupt Mask */
46 #define CREG_QMASK 0x18UL /* QEC Error Interrupt Mask */
47 #define CREG_BMASK 0x1cUL /* BigMAC Error Interrupt Mask*/
52 #define CREG_CCNT 0x30UL /* Collision Counter */
58 #define CREG_STAT_TXIRQ 0x00200000 /* Transmit Interrupt */
63 #define CREG_STAT_RXIRQ 0x00000020 /* Receive Interrupt */
87 /* 0x004-->0x0fc, reserved */
[all …]
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/graniterapids/
Dpipeline.json21 …counter. This event can approximate elapsed time while the core was not in a halt state. It is cou…
29 …counter. This event can approximate elapsed time while the core was not in a halt state. It is cou…
36 …e the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eigh…
48 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
51 …- an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside…
56 "BriefDescription": "Number of instructions retired. General Counter - architectural event",
60 …- an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside…
72 … the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end r…
75 …-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution…
80 …"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - archit…
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/freescale/
Dgianfar.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
13 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
16 * -Add support for module parameters
17 * -Add patch for ethtool phys id
27 #include <linux/interrupt.h>
67 #define DRV_NAME "gfar-enet"
92 #define GFAR_RXB_SIZE rounddown(GFAR_RXB_TRUESIZE - GFAR_SKBFRAG_OVR, 64)
95 #define TX_RING_MOD_MASK(size) (size-1)
96 #define RX_RING_MOD_MASK(size) (size-1)
108 * time described by a value of 1 in the interrupt
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/aquantia/atlantic/hw_atl/
Dhw_atl_llh.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) 2014-2019 aQuantia Corporation
5 * Copyright (C) 2019-2020 Marvell International Ltd.
59 /* get rx dma good octet counter */
62 /* get rx dma good packet counter */
65 /* get tx dma good octet counter */
68 /* get tx dma good packet counter */
71 /* get msm rx errors counter register */
74 /* get msm rx unicast frames counter register */
77 /* get msm rx multicast frames counter register */
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/aquantia/atlantic/hw_atl/
Dhw_atl_llh.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) 2014-2019 aQuantia Corporation
5 * Copyright (C) 2019-2020 Marvell International Ltd.
59 /* get rx dma good octet counter */
62 /* get rx dma good packet counter */
65 /* get tx dma good octet counter */
68 /* get tx dma good packet counter */
71 /* get msm rx errors counter register */
74 /* get msm rx unicast frames counter register */
77 /* get msm rx multicast frames counter register */
[all …]
/kernel/linux/linux-5.10/include/linux/platform_data/
Dmlxreg.h1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
3 * Copyright (C) 2017-2020 Mellanox Technologies Ltd.
14 * enum mlxreg_wdt_type - type of HW watchdog
28 * struct mlxreg_hotplug_device - I2C device data:
46 * struct mlxreg_core_data - attributes control data:
55 * @np - pointer to node platform associated with attribute;
56 * @hpdev - hotplug device data;
57 * @health_cntr: dynamic device health indication counter;
59 * @regnum: number of registers occupied by multi-register attribute;
77 * struct mlxreg_core_item - same type components controlled by the driver:
[all …]
/kernel/linux/linux-6.6/drivers/rtc/
Drtc-imxdi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
8 * This driver uses the 47-bit 32 kHz counter in the Freescale DryIce block
10 * Since the RTC framework performs API locking via rtc->ops_lock the
17 * DIER (DryIce Interrupt Enable Register) are the only exception. These
36 #define DTCMR 0x00 /* Time Counter MSB Reg */
37 #define DTCLR 0x04 /* Time Counter LSB Reg */
41 #define DCAMR_UNSET 0xFFFFFFFF /* doomsday - 1 sec */
44 #define DCR_TDCHL (1 << 30) /* Tamper-detect configuration hard lock */
45 #define DCR_TDCSL (1 << 29) /* Tamper-detect configuration soft lock */
[all …]
/kernel/linux/linux-5.10/drivers/rtc/
Drtc-imxdi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
8 * This driver uses the 47-bit 32 kHz counter in the Freescale DryIce block
10 * Since the RTC framework performs API locking via rtc->ops_lock the
17 * DIER (DryIce Interrupt Enable Register) are the only exception. These
35 #define DTCMR 0x00 /* Time Counter MSB Reg */
36 #define DTCLR 0x04 /* Time Counter LSB Reg */
40 #define DCAMR_UNSET 0xFFFFFFFF /* doomsday - 1 sec */
43 #define DCR_TDCHL (1 << 30) /* Tamper-detect configuration hard lock */
44 #define DCR_TDCSL (1 << 29) /* Tamper-detect configuration soft lock */
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