| /kernel/linux/linux-5.10/drivers/net/ipa/ |
| D | ipa_interrupt.c | 9 * The IPA has an interrupt line distinct from the interrupt used by the GSI
13 * embedded in the IPA. Each IPA interrupt type can be both masked and
23 #include <linux/interrupt.h>
32 * struct ipa_interrupt - IPA interrupt information
36 * @handler: Array of handlers indexed by IPA interrupt ID
45 /* Returns true if the interrupt type is associated with the microcontroller */
46 static bool ipa_interrupt_uc(struct ipa_interrupt *interrupt, u32 irq_id) in ipa_interrupt_uc() argument
51 /* Process a particular interrupt type that has been received */
52 static void ipa_interrupt_process(struct ipa_interrupt *interrupt, u32 irq_id) in ipa_interrupt_process() argument
54 bool uc_irq = ipa_interrupt_uc(interrupt, irq_id); in ipa_interrupt_process()
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| D | ipa_interrupt.h | 16 * enum ipa_irq_id - IPA interrupt type
17 * @IPA_IRQ_UC_0: Microcontroller event interrupt
18 * @IPA_IRQ_UC_1: Microcontroller response interrupt
19 * @IPA_IRQ_TX_SUSPEND: Data ready interrupt
21 * The data ready interrupt is signaled if data has arrived that is destined
28 IPA_IRQ_COUNT, /* Number of interrupt types (not an index) */
32 * typedef ipa_irq_handler_t - IPA interrupt handler function type
34 * @irq_id: interrupt type
37 * IPA interrupt type
42 * ipa_interrupt_add() - Register a handler for an IPA interrupt type
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | ti,c64x+megamod-pic.txt | 1 C6X Interrupt Chips
4 * C64X+ Core Interrupt Controller
6 The core interrupt controller provides 16 prioritized interrupts to the
8 Priority 2 and 3 are reserved. Priority 4-15 are used for interrupt
14 - #interrupt-cells: <1>
16 Interrupt Specifier Definition
18 Single cell specifying the core interrupt priority level (4-15) where
23 core_pic: interrupt-controller@0 {
24 interrupt-controller;
25 #interrupt-cells = <1>;
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| D | samsung,exynos4210-combiner.txt | 1 * Samsung Exynos Interrupt Combiner Controller
3 Samsung's Exynos4 architecture includes a interrupt combiner controller which
4 can combine interrupt sources as a group and provide a single interrupt request
5 for the group. The interrupt request from each group are connected to a parent
6 interrupt controller, such as GIC in case of Exynos4210.
8 The interrupt combiner controller consists of multiple combiners. Up to eight
9 interrupt sources can be connected to a combiner. The combiner outputs one
10 combined interrupt for its eight interrupt sources. The combined interrupt
11 is usually connected to a parent interrupt controller.
13 A single node in the device tree is used to describe the interrupt combiner
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| D | interrupts.txt | 1 Specifying interrupt information for devices
4 1) Interrupt client nodes
11 properties contain a list of interrupt specifiers, one per output interrupt. The
12 format of the interrupt specifier is determined by the interrupt controller to
16 interrupt-parent = <&intc1>;
19 The "interrupt-parent" property is used to specify the controller to which
20 interrupts are routed and contains a single phandle referring to the interrupt
22 interrupt client node or in any of its parent nodes. Interrupts listed in the
23 "interrupts" property are always in reference to the node's interrupt parent.
26 to reference multiple interrupt parents or a different interrupt parent than
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| D | marvell,icu.txt | 1 Marvell ICU Interrupt Controller
4 The Marvell ICU (Interrupt Consolidation Unit) controller is
5 responsible for collecting all wired-interrupt sources in the CP and
6 communicating them to the GIC in the AP, the unit translates interrupt
17 Subnodes: Each group of interrupt is declared as a subnode of the ICU,
28 - #interrupt-cells: Specifies the number of cells needed to encode an
29 interrupt source. The value shall be 2.
31 The 1st cell is the index of the interrupt in the ICU unit.
33 The 2nd cell is the type of the interrupt. See arm,gic.txt for
36 - interrupt-controller: Identifies the node as an interrupt
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/interrupt-controller/ |
| D | renesas,rzg2l-irqc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/renesas,rzg2l-irqc.yaml#
7 title: Renesas RZ/G2L (and alike SoC's) Interrupt Controller (IA55)
14 IA55 performs various interrupt controls including synchronization for the external
16 interrupts output by each IP. And it notifies the interrupt to the GIC
18 - GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts
31 '#interrupt-cells':
33 include/dt-bindings/interrupt-controller/irqc-rzg2l.h and the second
40 interrupt-controller: true
48 - description: NMI interrupt
49 - description: IRQ0 interrupt
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| D | interrupts.txt | 1 Specifying interrupt information for devices
4 1) Interrupt client nodes
11 properties contain a list of interrupt specifiers, one per output interrupt. The
12 format of the interrupt specifier is determined by the interrupt controller to
16 interrupt-parent = <&intc1>;
19 The "interrupt-parent" property is used to specify the controller to which
20 interrupts are routed and contains a single phandle referring to the interrupt
22 interrupt client node or in any of its parent nodes. Interrupts listed in the
23 "interrupts" property are always in reference to the node's interrupt parent.
26 to reference multiple interrupt parents or a different interrupt parent than
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| D | marvell,icu.txt | 1 Marvell ICU Interrupt Controller
4 The Marvell ICU (Interrupt Consolidation Unit) controller is
5 responsible for collecting all wired-interrupt sources in the CP and
6 communicating them to the GIC in the AP, the unit translates interrupt
17 Subnodes: Each group of interrupt is declared as a subnode of the ICU,
28 - #interrupt-cells: Specifies the number of cells needed to encode an
29 interrupt source. The value shall be 2.
31 The 1st cell is the index of the interrupt in the ICU unit.
33 The 2nd cell is the type of the interrupt. See arm,gic.txt for
36 - interrupt-controller: Identifies the node as an interrupt
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| D | samsung,exynos4210-combiner.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/samsung,exynos4210-combiner.yaml#
7 title: Samsung Exynos SoC Interrupt Combiner Controller
13 Samsung's Exynos4 architecture includes a interrupt combiner controller which
14 can combine interrupt sources as a group and provide a single interrupt
15 request for the group. The interrupt request from each group are connected to
16 a parent interrupt controller, such as GIC in case of Exynos4210.
18 The interrupt combiner controller consists of multiple combiners. Up to eight
19 interrupt sources can be connected to a combiner. The combiner outputs one
20 combined interrupt for its eight interrupt sources. The combined interrupt is
21 usually connected to a parent interrupt controller.
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | mpic.txt | 2 Freescale MPIC Interrupt Controller Node
6 The Freescale MPIC interrupt controller is found on all PowerQUICC
9 additional cells in the interrupt specifier defining interrupt type
29 - interrupt-controller
32 Definition: Specifies that this node is an interrupt
35 - #interrupt-cells
38 Definition: Shall be 2 or 4. A value of 2 means that interrupt
39 specifiers do not contain the interrupt-type or type-specific
52 the boot program has initialized all interrupt source
57 that any initialization related to interrupt sources shall
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | mpic.txt | 2 Freescale MPIC Interrupt Controller Node
6 The Freescale MPIC interrupt controller is found on all PowerQUICC
9 additional cells in the interrupt specifier defining interrupt type
29 - interrupt-controller
32 Definition: Specifies that this node is an interrupt
35 - #interrupt-cells
38 Definition: Shall be 2 or 4. A value of 2 means that interrupt
39 specifiers do not contain the interrupt-type or type-specific
52 the boot program has initialized all interrupt source
57 that any initialization related to interrupt sources shall
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/wireless/ |
| D | qcom,ath11k.yaml | 32 interrupt-names:
101 - description: misc-pulse1 interrupt events
102 - description: misc-latch interrupt events
103 - description: sw exception interrupt events
104 - description: watchdog interrupt events
105 - description: interrupt event for ring CE0
106 - description: interrupt event for ring CE1
107 - description: interrupt event for ring CE2
108 - description: interrupt event for ring CE3
109 - description: interrupt event for ring CE4
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/ivsrcid/dcn/ |
| D | irqsrcs_dcn_1_0.h | 78 #define DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT0_STATUS 2 // DCCG perfmon counter0 interrupt DCCG_PERF…
81 #define DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT1_STATUS 2 // DCCG perfmon counter1 interrupt DCCG_PERF…
84 #define DCN_1_0__SRCID__DMU_PERFCOUNTER_INT0_STATUS 3 // DMU perfmon counter0 interrupt DMU_PERFMON…
87 #define DCN_1_0__SRCID__DMU_PERFCOUNTER_INT1_STATUS 3 // DMU perfmon counter1 interrupt DMU_PERFMON…
90 #define DCN_1_0__SRCID__DIO_PERFCOUNTER_INT0_STATUS 4 // DIO perfmon counter0 interrupt DIO_PERFMON…
93 #define DCN_1_0__SRCID__DIO_PERFCOUNTER_INT1_STATUS 4 // DIO perfmon counter1 interrupt DIO_PERFMON…
96 #define DCN_1_0__SRCID__RBBMIF_TIMEOUT_INT 5 // RBBMIF timeout interrupt RBBMIF_IHC_TIMEOUT…
102 #define DCN_1_0__SRCID__DMCU_SCP_INT 5 // DMCU Slave Communication Port Interrupt DMCU…
105 #define DCN_1_0__SRCID__DMCU_ABM0_HG_READY_INT 6 // ABM histogram ready interrupt ABM0_HG_READY…
108 #define DCN_1_0__SRCID__DMCU_ABM0_LS_READY_INT 6 // ABM luma stat ready interrupt ABM0_LS_READY…
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/ivsrcid/dcn/ |
| D | irqsrcs_dcn_1_0.h | 78 #define DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT0_STATUS 2 // DCCG perfmon counter0 interrupt DCCG_PERF…
81 #define DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT1_STATUS 2 // DCCG perfmon counter1 interrupt DCCG_PERF…
84 #define DCN_1_0__SRCID__DMU_PERFCOUNTER_INT0_STATUS 3 // DMU perfmon counter0 interrupt DMU_PERFMON…
87 #define DCN_1_0__SRCID__DMU_PERFCOUNTER_INT1_STATUS 3 // DMU perfmon counter1 interrupt DMU_PERFMON…
90 #define DCN_1_0__SRCID__DIO_PERFCOUNTER_INT0_STATUS 4 // DIO perfmon counter0 interrupt DIO_PERFMON…
93 #define DCN_1_0__SRCID__DIO_PERFCOUNTER_INT1_STATUS 4 // DIO perfmon counter1 interrupt DIO_PERFMON…
96 #define DCN_1_0__SRCID__RBBMIF_TIMEOUT_INT 5 // RBBMIF timeout interrupt RBBMIF_IHC_TIMEOUT…
102 #define DCN_1_0__SRCID__DMCU_SCP_INT 5 // DMCU Slave Communication Port Interrupt DMCU…
105 #define DCN_1_0__SRCID__DMCU_ABM0_HG_READY_INT 6 // ABM histogram ready interrupt ABM0_HG_READY…
108 #define DCN_1_0__SRCID__DMCU_ABM0_LS_READY_INT 6 // ABM luma stat ready interrupt ABM0_LS_READY…
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| /kernel/liteos_a/arch/arm/include/ |
| D | los_hwi.h | 33 * @defgroup los_hwi Hardware interrupt
57 * An interrupt is active.
69 * An interrupt is inactive.
75 * Highest priority of a hardware interrupt.
81 * Lowest priority of a hardware interrupt.
87 * Max name length of a hardware interrupt.
93 * Hardware interrupt error code: Invalid interrupt number.
97 * Solution: Ensure that the interrupt number is valid.
103 * Hardware interrupt error code: Null hardware interrupt handling function.
107 * Solution: Pass in a valid non-null hardware interrupt handling function.
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| /kernel/linux/linux-5.10/arch/mips/boot/dts/loongson/ |
| D | ls7a-pch.dtsi | 13 pic: interrupt-controller@10000000 {
16 interrupt-controller;
17 interrupt-parent = <&htvec>;
19 #interrupt-cells = <2>;
26 interrupt-parent = <&pic>;
36 interrupt-parent = <&pic>;
46 interrupt-parent = <&pic>;
56 interrupt-parent = <&pic>;
66 #interrupt-cells = <2>;
83 interrupt-parent = <&pic>;
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| /kernel/linux/linux-5.10/arch/powerpc/boot/dts/ |
| D | fsp2.dts | 64 #interrupt-cells = <2>;
66 interrupt-controller;
76 #interrupt-cells = <2>;
79 interrupt-controller;
82 interrupt-parent = <&UIC0>;
90 #interrupt-cells = <2>;
93 interrupt-controller;
96 interrupt-parent = <&UIC0>;
104 #interrupt-cells = <2>;
107 interrupt-controller;
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| /kernel/linux/linux-6.6/arch/powerpc/boot/dts/ |
| D | fsp2.dts | 64 #interrupt-cells = <2>;
66 interrupt-controller;
76 #interrupt-cells = <2>;
79 interrupt-controller;
82 interrupt-parent = <&UIC0>;
90 #interrupt-cells = <2>;
93 interrupt-controller;
96 interrupt-parent = <&UIC0>;
104 #interrupt-cells = <2>;
107 interrupt-controller;
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| /kernel/linux/linux-6.6/drivers/net/ipa/ |
| D | ipa_interrupt.c | 9 * The IPA has an interrupt line distinct from the interrupt used by the GSI
13 * embedded in the IPA. Each IPA interrupt type can be both masked and
23 #include <linux/interrupt.h>
35 * struct ipa_interrupt - IPA interrupt information
46 /* Process a particular interrupt type that has been received */
47 static void ipa_interrupt_process(struct ipa_interrupt *interrupt, u32 irq_id) in ipa_interrupt_process() argument
49 struct ipa *ipa = interrupt->ipa; in ipa_interrupt_process()
60 /* For microcontroller interrupts, clear the interrupt right in ipa_interrupt_process()
68 /* Clearing the SUSPEND_TX interrupt also clears the in ipa_interrupt_process()
70 * caused the interrupt, so defer clearing until after in ipa_interrupt_process()
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| D | ipa_interrupt.h | 18 * @interrupt: IPA interrupt structure
19 * @endpoint_id: Endpoint whose interrupt should be enabled
22 * A TX_SUSPEND interrupt arrives on an AP RX enpoint when packet data can't
26 void ipa_interrupt_suspend_enable(struct ipa_interrupt *interrupt,
31 * @interrupt: IPA interrupt structure
32 * @endpoint_id: Endpoint whose interrupt should be disabled
34 void ipa_interrupt_suspend_disable(struct ipa_interrupt *interrupt,
39 * @interrupt: IPA interrupt structure
41 * Clear the TX_SUSPEND interrupt for all endpoints that signaled it.
43 void ipa_interrupt_suspend_clear_all(struct ipa_interrupt *interrupt);
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| /kernel/liteos_m/arch/risc-v/riscv32/gcc/ |
| D | los_arch_interrupt.h | 48 * Define the type of a hardware interrupt vector table function.
73 * Highest priority of a hardware interrupt.
79 * Lowest priority of a hardware interrupt.
85 * Count of HimiDeer system interrupt vector.
91 * Count of HimiDeer local interrupt vector 0 - 5, enabled by CSR mie 26 -31 bit.
97 * Count of HimiDeer local interrupt vector 6 - 31, enabled by custom CSR locie0 0 - 25 bit.
103 * Count of HimiDeer local IRQ interrupt vector.
109 * Count of himideer interrupt vector.
115 * Count of risc-v system interrupt vector.
126 * Maximum interrupt number.
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| /kernel/linux/linux-5.10/arch/mips/boot/dts/brcm/ |
| D | bcm7358.dtsi | 24 cpu_intc: interrupt-controller {
26 compatible = "mti,cpu-interrupt-controller";
28 interrupt-controller;
29 #interrupt-cells = <1>;
53 periph_intc: interrupt-controller@411400 {
57 interrupt-controller;
58 #interrupt-cells = <1>;
60 interrupt-parent = <&cpu_intc>;
64 sun_l2_intc: interrupt-controller@403000 {
67 interrupt-controller;
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| /kernel/linux/linux-6.6/arch/mips/boot/dts/brcm/ |
| D | bcm7358.dtsi | 24 cpu_intc: interrupt-controller {
26 compatible = "mti,cpu-interrupt-controller";
28 interrupt-controller;
29 #interrupt-cells = <1>;
53 periph_intc: interrupt-controller@411400 {
57 interrupt-controller;
58 #interrupt-cells = <1>;
60 interrupt-parent = <&cpu_intc>;
64 sun_l2_intc: interrupt-controller@403000 {
67 interrupt-controller;
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| /kernel/liteos_m/arch/risc-v/nuclei/gcc/nmsis/Core/Include/ |
| D | core_feature_eclic.h | 26 …* 1. __ECLIC_PRESENT: Define whether Enhanced Core Local Interrupt Controller (ECLIC) Unit is pre…
32 * 4. __ECLIC_INTNUM : Define the external interrupt number of ECLIC Unit
67 …uint32_t numint:13; /*!< bit: 0..12 number of maximum interrupt inputs supp…
76 * \brief Access to the structure of a vector interrupt controller.
79 …__IOM uint8_t INTIP; /*!< Offset: 0x000 (R/W) Interrupt set pending regist…
80 …__IOM uint8_t INTIE; /*!< Offset: 0x001 (R/W) Interrupt set enable registe…
81 …__IOM uint8_t INTATTR; /*!< Offset: 0x002 (R/W) Interrupt set attributes reg…
82 …__IOM uint8_t INTCTRL; /*!< Offset: 0x003 (R/W) Interrupt configure register…
122 …UPT 0x0 /*!< Non-Vector Interrupt Mode of ECLIC */
123 …UPT 0x1 /*!< Vector Interrupt Mode of ECLIC */
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