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/kernel/linux/linux-5.10/drivers/irqchip/
Dirq-ti-sci-intr.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/
21 * struct ti_sci_intr_irq_domain - Structure representing a TISCI based
24 * @out_irqs: TISCI resource pointer representing INTR irqs.
26 * @ti_sci_id: TI-SCI device identifier
27 * @type: Specifies the trigger type supported by this Interrupt Router
34 u32 type; member
38 .name = "INTR",
48 * ti_sci_intr_irq_domain_translate() - Retrieve hwirq and type from
53 * @type: IRQ type
[all …]
/kernel/linux/linux-6.6/drivers/irqchip/
Dirq-ti-sci-intr.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/
21 * struct ti_sci_intr_irq_domain - Structure representing a TISCI based
24 * @out_irqs: TISCI resource pointer representing INTR irqs.
26 * @ti_sci_id: TI-SCI device identifier
27 * @type: Specifies the trigger type supported by this Interrupt Router
34 u32 type; member
38 .name = "INTR",
48 * ti_sci_intr_irq_domain_translate() - Retrieve hwirq and type from
53 * @type: IRQ type
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Dti,sci-intr.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/ti,sci-intr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lokesh Vutla <lokeshvutla@ti.com>
13 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
16 The Interrupt Router (INTR) module provides a mechanism to mux M
22 +----------------------+
24 +-------+ | +------+ +-----+ |
25 | GPIO |----------->| | irq0 | | 0 | | Host IRQ
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/interrupt-controller/
Dti,sci-intr.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/ti,sci-intr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lokesh Vutla <lokeshvutla@ti.com>
13 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
16 The Interrupt Router (INTR) module provides a mechanism to mux M
22 +----------------------+
24 +-------+ | +------+ +-----+ |
25 | GPIO |----------->| | irq0 | | 0 | | Host IRQ
[all …]
/kernel/linux/linux-5.10/drivers/parisc/
Diosapic_private.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Copyright (C) 2000,2003 Grant Grundler (grundler at parisc-linux.org)
7 * Copyright (C) 2002 Matthew Wilcox (willy at parisc-linux.org)
15 ** they pack nicely for 64-bit compilation. (ie sizeof(long) == 8)
21 ** -----------------------
24 ** table per cell. N- and L-class consist of a single cell.
28 /* Entry Type 139 identifies an I/O SAPIC interrupt entry */
35 ** Interrupt Type of 0 indicates a vectored interrupt,
47 ** Trigger mode of SAPIC I/O input signals:
49 ** 01 = Edge-triggered
[all …]
/kernel/linux/linux-6.6/drivers/parisc/
Diosapic_private.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Copyright (C) 2000,2003 Grant Grundler (grundler at parisc-linux.org)
7 * Copyright (C) 2002 Matthew Wilcox (willy at parisc-linux.org)
15 ** they pack nicely for 64-bit compilation. (ie sizeof(long) == 8)
21 ** -----------------------
24 ** table per cell. N- and L-class consist of a single cell.
28 /* Entry Type 139 identifies an I/O SAPIC interrupt entry */
35 ** Interrupt Type of 0 indicates a vectored interrupt,
47 ** Trigger mode of SAPIC I/O input signals:
49 ** 01 = Edge-triggered
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/ti/
Dk3-am65-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "ti,am654-sci";
11 ti,host-id = <12>;
12 #address-cells = <1>;
13 #size-cells = <1>;
16 mbox-names = "rx", "tx";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
[all …]
Dk3-j7200-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 atf-sram@0 {
21 scm_conf: scm-conf@100000 {
22 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
24 #address-cells = <1>;
25 #size-cells = <1>;
[all …]
Dk3-j721e-mcu-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
27 compatible = "ti,k2g-sci-clk";
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/ti/
Dk3-am65-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
9 dmsc: system-controller@44083000 {
10 compatible = "ti,am654-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
[all …]
Dk3-am62a-mcu.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "pinctrl-single";
12 #pinctrl-cells = <1>;
13 pinctrl-single,register-width = <32>;
14 pinctrl-single,function-mask = <0xffffffff>;
24 compatible = "ti,am654-timer";
27 clock-names = "fck";
28 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
29 ti,timer-pwm;
[all …]
Dk3-am64-mcu.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
15 compatible = "ti,am654-timer";
18 clock-names = "fck";
19 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
20 ti,timer-pwm;
25 compatible = "ti,am654-timer";
28 clock-names = "fck";
29 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
30 ti,timer-pwm;
[all …]
Dk3-am62-mcu.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "pinctrl-single";
12 #pinctrl-cells = <1>;
13 pinctrl-single,register-width = <32>;
14 pinctrl-single,function-mask = <0xffffffff>;
18 compatible = "ti,j721e-esm";
20 ti,esm-pins = <0>, <1>, <2>, <85>;
29 compatible = "ti,am654-timer";
32 clock-names = "fck";
[all …]
/kernel/linux/linux-6.6/drivers/tty/serial/jsm/
Djsm_neo.c1 // SPDX-License-Identifier: GPL-2.0+
25 * a non-destructive, read-only location on the Neo card.
27 * In this case, we are reading the DVID (Read-only Device Identification)
32 readb(bd->re_map_membase + 0x8D); in neo_pci_posting_flush()
38 ier = readb(&ch->ch_neo_uart->ier); in neo_set_cts_flow_control()
39 efr = readb(&ch->ch_neo_uart->efr); in neo_set_cts_flow_control()
41 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting CTSFLOW\n"); in neo_set_cts_flow_control()
51 writeb(0, &ch->ch_neo_uart->efr); in neo_set_cts_flow_control()
54 writeb(efr, &ch->ch_neo_uart->efr); in neo_set_cts_flow_control()
57 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr); in neo_set_cts_flow_control()
[all …]
/kernel/linux/linux-5.10/drivers/tty/serial/jsm/
Djsm_neo.c1 // SPDX-License-Identifier: GPL-2.0+
25 * a non-destructive, read-only location on the Neo card.
27 * In this case, we are reading the DVID (Read-only Device Identification)
32 readb(bd->re_map_membase + 0x8D); in neo_pci_posting_flush()
38 ier = readb(&ch->ch_neo_uart->ier); in neo_set_cts_flow_control()
39 efr = readb(&ch->ch_neo_uart->efr); in neo_set_cts_flow_control()
41 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting CTSFLOW\n"); in neo_set_cts_flow_control()
51 writeb(0, &ch->ch_neo_uart->efr); in neo_set_cts_flow_control()
54 writeb(efr, &ch->ch_neo_uart->efr); in neo_set_cts_flow_control()
57 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr); in neo_set_cts_flow_control()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/engine/
Dfalcon.c32 struct nvkm_falcon *falcon = nvkm_falcon(oclass->engine); in nvkm_falcon_oclass_get()
35 while (falcon->func->sclass[c].oclass) { in nvkm_falcon_oclass_get()
37 oclass->base = falcon->func->sclass[index]; in nvkm_falcon_oclass_get()
49 return nvkm_gpuobj_new(object->engine->subdev.device, 256, in nvkm_falcon_cclass_bind()
62 struct nvkm_subdev *subdev = &falcon->engine.subdev; in nvkm_falcon_intr()
63 struct nvkm_device *device = subdev->device; in nvkm_falcon_intr()
64 const u32 base = falcon->addr; in nvkm_falcon_intr()
66 u32 intr = nvkm_rd32(device, base + 0x008) & dest & ~(dest >> 16); in nvkm_falcon_intr() local
73 if (intr & 0x00000040) { in nvkm_falcon_intr()
74 if (falcon->func->intr) { in nvkm_falcon_intr()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/subdev/timer/
Dbase.c29 struct nvkm_subdev *subdev = &wait->tmr->subdev; in nvkm_timer_wait_test()
30 u64 time = nvkm_timer_read(wait->tmr); in nvkm_timer_wait_test()
32 if (wait->reads == 0) { in nvkm_timer_wait_test()
33 wait->time0 = time; in nvkm_timer_wait_test()
34 wait->time1 = time; in nvkm_timer_wait_test()
37 if (wait->time1 == time) { in nvkm_timer_wait_test()
38 if (wait->reads++ == 16) { in nvkm_timer_wait_test()
40 return -ETIMEDOUT; in nvkm_timer_wait_test()
43 wait->time1 = time; in nvkm_timer_wait_test()
44 wait->reads = 1; in nvkm_timer_wait_test()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
Dgf100.c43 nvkm_wr32(chan->cgrp->runl->fifo->engine.subdev.device, 0x002634, chan->id); in gf100_chan_preempt()
49 struct nvkm_device *device = chan->cgrp->runl->fifo->engine.subdev.device; in gf100_chan_stop()
51 nvkm_mask(device, 0x003004 + (chan->id * 8), 0x00000001, 0x00000000); in gf100_chan_stop()
57 struct nvkm_device *device = chan->cgrp->runl->fifo->engine.subdev.device; in gf100_chan_start()
59 nvkm_wr32(device, 0x003004 + (chan->id * 8), 0x001f0001); in gf100_chan_start()
67 struct nvkm_fifo *fifo = chan->cgrp->runl->fifo; in gf100_chan_unbind()
68 struct nvkm_device *device = fifo->engine.subdev.device; in gf100_chan_unbind()
70 /*TODO: Is this cargo-culted, or necessary? RM does *something* here... Why? */ in gf100_chan_unbind()
73 nvkm_wr32(device, 0x003000 + (chan->id * 8), 0x00000000); in gf100_chan_unbind()
79 struct nvkm_device *device = chan->cgrp->runl->fifo->engine.subdev.device; in gf100_chan_bind()
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/pensando/ionic/
Dionic_dev.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
19 mod_timer(&ionic->watchdog_timer, in ionic_watchdog_cb()
20 round_jiffies(jiffies + ionic->watchdog_period)); in ionic_watchdog_cb()
22 if (!ionic->lif) in ionic_watchdog_cb()
28 ionic_link_status_check_request(ionic->lif, false); in ionic_watchdog_cb()
33 struct ionic_dev *idev = &ionic->idev; in ionic_init_devinfo()
35 idev->dev_info.asic_type = ioread8(&idev->dev_info_regs->asic_type); in ionic_init_devinfo()
36 idev->dev_info.asic_rev = ioread8(&idev->dev_info_regs->asic_rev); in ionic_init_devinfo()
38 memcpy_fromio(idev->dev_info.fw_version, in ionic_init_devinfo()
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/pensando/ionic/
Dionic_dev.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
17 struct ionic_lif *lif = ionic->lif; in ionic_watchdog_cb()
21 mod_timer(&ionic->watchdog_timer, in ionic_watchdog_cb()
22 round_jiffies(jiffies + ionic->watchdog_period)); in ionic_watchdog_cb()
28 dev_dbg(ionic->dev, "%s: hb %d running %d UP %d\n", in ionic_watchdog_cb()
29 __func__, hb, netif_running(lif->netdev), in ionic_watchdog_cb()
30 test_bit(IONIC_LIF_F_UP, lif->state)); in ionic_watchdog_cb()
33 !test_bit(IONIC_LIF_F_FW_RESET, lif->state)) in ionic_watchdog_cb()
36 if (test_bit(IONIC_LIF_F_FILTER_SYNC_NEEDED, lif->state) && in ionic_watchdog_cb()
[all …]
/kernel/linux/linux-5.10/drivers/mfd/
Dasic3.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Copyright 2004-2005 Phil Blundell
9 * Copyright 2007-2008 OpenedHand Ltd.
92 iowrite16(value, asic->mapping + in asic3_write_register()
93 (reg >> asic->bus_shift)); in asic3_write_register()
99 return ioread16(asic->mapping + in asic3_read_register()
100 (reg >> asic->bus_shift)); in asic3_read_register()
109 raw_spin_lock_irqsave(&asic->lock, flags); in asic3_set_register()
116 raw_spin_unlock_irqrestore(&asic->lock, flags); in asic3_set_register()
122 (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/intel/igc/
Digc_defines.h1 /* SPDX-License-Identifier: GPL-2.0 */
47 /* Loop limit on how long we wait for auto-negotiation to complete */
125 /* 1000BASE-T Control Register */
130 /* 1000BASE-T Status Register */
146 /* NVM Addressing bits based on type 0=small, 1=large */
195 /* 1Gbps and 2.5Gbps half duplex is not supported, nor spec-compliant. */
218 #define IGC_ICR_RXT0 BIT(7) /* Rx timer intr (ring 0) */
225 #define IGC_ICS_RXT0 IGC_ICR_RXT0 /* Rx timer intr */
240 #define IGC_IMS_RXT0 IGC_ICR_RXT0 /* Rx timer intr */
244 #define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/intel/igc/
Digc_defines.h1 /* SPDX-License-Identifier: GPL-2.0 */
88 /* Loop limit on how long we wait for auto-negotiation to complete */
170 /* 1000BASE-T Control Register */
174 /* 1000BASE-T Status Register */
189 /* NVM Addressing bits based on type 0=small, 1=large */
238 /* 1Gbps and 2.5Gbps half duplex is not supported, nor spec-compliant. */
261 #define IGC_ICR_RXT0 BIT(7) /* Rx timer intr (ring 0) */
268 #define IGC_ICS_RXT0 IGC_ICR_RXT0 /* Rx timer intr */
283 #define IGC_IMS_RXT0 IGC_ICR_RXT0 /* Rx timer intr */
287 #define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_encoder.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
31 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
34 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
37 (p) ? (p)->parent->base.id : -1, \
38 (p) ? (p)->intf_idx - INTF_0 : -1, \
39 (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
43 (p) ? (p)->parent->base.id : -1, \
44 (p) ? (p)->intf_idx - INTF_0 : -1, \
45 (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
[all …]
/kernel/linux/linux-5.10/drivers/iio/accel/
Dbmc150-accel-core.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * 3-axis accelerometer driver supporting following Bosch-Sensortec chips:
4 * - BMC150
5 * - BMI055
6 * - BMA255
7 * - BMA250E
8 * - BMA222E
9 * - BMA280
26 #include <linux/iio/trigger.h>
31 #include "bmc150-accel.h"
[all …]

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