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/kernel/linux/linux-6.6/drivers/net/ethernet/aquantia/atlantic/hw_atl/
Dhw_atl_llh_internal.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) 2014-2019 aQuantia Corporation
5 * Copyright (C) 2019-2020 Marvell International Ltd.
50 /* register address for bitfield rx dma good octet counter lsw [1f:0] */
52 /* register address for bitfield rx dma good packet counter lsw [1f:0] */
59 /* register address for bitfield rx dma good octet counter msw [3f:20] */
61 /* register address for bitfield rx dma good packet counter msw [3f:20] */
68 /* preprocessor definitions for msm rx errors counter register */
71 /* preprocessor definitions for msm rx unicast frames counter register */
74 /* preprocessor definitions for msm rx multicast frames counter register */
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/aquantia/atlantic/hw_atl/
Dhw_atl_llh_internal.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) 2014-2019 aQuantia Corporation
5 * Copyright (C) 2019-2020 Marvell International Ltd.
50 /* register address for bitfield rx dma good octet counter lsw [1f:0] */
52 /* register address for bitfield rx dma good packet counter lsw [1f:0] */
59 /* register address for bitfield rx dma good octet counter msw [3f:20] */
61 /* register address for bitfield rx dma good packet counter msw [3f:20] */
68 /* preprocessor definitions for msm rx errors counter register */
71 /* preprocessor definitions for msm rx unicast frames counter register */
74 /* preprocessor definitions for msm rx multicast frames counter register */
[all …]
/kernel/linux/linux-6.6/arch/riscv/boot/dts/starfive/
Djh7110-starfive-visionfive-2-v1.3b.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include "jh7110-starfive-visionfive-2.dtsi"
12 compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
16 starfive,tx-use-rgmii-clk;
17 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
18 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
22 starfive,tx-use-rgmii-clk;
23 assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
24 assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Dmotorcomm,yt8xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Sae <frank.sae@motor-comm.com>
13 - $ref: ethernet-phy.yaml#
18 - ethernet-phy-id4f51.e91a
19 - ethernet-phy-id4f51.e91b
21 rx-internal-delay-ps:
23 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
24 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/aquantia/atlantic/hw_atl2/
Dhw_atl2_llh_internal.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 /* RX pif_rpf_redir_2_en_i Bitfield Definitions
19 /* RX pif_rpf_rss_hash_type_i Bitfield Definitions
27 /* rx rpf_new_rpf_en bitfield definitions
36 /* inverted bitmask for bitfield rpf_new_rpf_en */
45 /* rx l2_uc_req_tag0{f}[5:0] bitfield definitions
55 /* inverted bitmask for bitfield l2_uc_req_tag0{f}[2:0] */
73 /* inverted bitmask for bitfield rpf_l2_bc_req_tag */
82 /* rx rpf_rss_red1_data_[4:0] bitfield definitions
99 /* rx vlan_req_tag0{f}[3:0] bitfield definitions
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/aquantia/atlantic/hw_atl2/
Dhw_atl2_llh_internal.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 /* RX pif_rpf_redir_2_en_i Bitfield Definitions
19 /* RX pif_rpf_rss_hash_type_i Bitfield Definitions
27 /* rx rpf_new_rpf_en bitfield definitions
36 /* inverted bitmask for bitfield rpf_new_rpf_en */
45 /* rx l2_uc_req_tag0{f}[5:0] bitfield definitions
55 /* inverted bitmask for bitfield l2_uc_req_tag0{f}[2:0] */
73 /* inverted bitmask for bitfield rpf_l2_bc_req_tag */
82 /* rx rpf_rss_red1_data_[4:0] bitfield definitions
99 /* rx vlan_req_tag0{f}[3:0] bitfield definitions
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/serial/
Dfsl-imx-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/fsl-imx-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabio Estevam <festevam@gmail.com>
13 - $ref: serial.yaml#
14 - $ref: rs485.yaml#
19 - const: fsl,imx1-uart
20 - const: fsl,imx21-uart
21 - items:
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/serial/
Dfsl-imx-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/fsl-imx-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabio Estevam <fabio.estevam@nxp.com>
13 - $ref: "serial.yaml"
14 - $ref: "rs485.yaml"
19 - const: fsl,imx1-uart
20 - const: fsl,imx21-uart
21 - items:
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/
Deiger.dts11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
30 #address-cells = <1>;
31 #size-cells = <0>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
39 i-cache-line-size = <32>;
40 d-cache-line-size = <32>;
[all …]
Darches.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
17 /dts-v1/;
20 #address-cells = <2>;
21 #size-cells = <1>;
24 dcr-parent = <&{/cpus/cpu@0}>;
34 #address-cells = <1>;
35 #size-cells = <0>;
41 clock-frequency = <0>; /* Filled in by U-Boot */
42 timebase-frequency = <0>; /* Filled in by U-Boot */
43 i-cache-line-size = <32>;
[all …]
Dklondike.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
12 #address-cells = <1>;
13 #size-cells = <1>;
16 dcr-parent = <&{/cpus/cpu@0}>;
24 #address-cells = <1>;
25 #size-cells = <0>;
31 clock-frequency = <300000000>; /* Filled in by U-Boot */
32 timebase-frequency = <300000000>; /* Filled in by U-Boot */
33 i-cache-line-size = <32>;
[all …]
Dglacier.dts4 * Copyright 2008-2010 DENX Software Engineering, Stefan Roese <sr@denx.de>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
30 #address-cells = <1>;
31 #size-cells = <0>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
39 i-cache-line-size = <32>;
[all …]
Dobs600.dts8 * Copyright 2007-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
15 /dts-v1/;
18 #address-cells = <1>;
19 #size-cells = <1>;
22 dcr-parent = <&{/cpus/cpu@0}>;
32 #address-cells = <1>;
33 #size-cells = <0>;
39 clock-frequency = <0>; /* Filled in by U-Boot */
40 timebase-frequency = <0>; /* Filled in by U-Boot */
41 i-cache-line-size = <32>;
[all …]
/kernel/linux/linux-6.6/arch/powerpc/boot/dts/
Deiger.dts11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
30 #address-cells = <1>;
31 #size-cells = <0>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
39 i-cache-line-size = <32>;
40 d-cache-line-size = <32>;
[all …]
Darches.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
17 /dts-v1/;
20 #address-cells = <2>;
21 #size-cells = <1>;
24 dcr-parent = <&{/cpus/cpu@0}>;
34 #address-cells = <1>;
35 #size-cells = <0>;
41 clock-frequency = <0>; /* Filled in by U-Boot */
42 timebase-frequency = <0>; /* Filled in by U-Boot */
43 i-cache-line-size = <32>;
[all …]
Dklondike.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
12 #address-cells = <1>;
13 #size-cells = <1>;
16 dcr-parent = <&{/cpus/cpu@0}>;
24 #address-cells = <1>;
25 #size-cells = <0>;
31 clock-frequency = <300000000>; /* Filled in by U-Boot */
32 timebase-frequency = <300000000>; /* Filled in by U-Boot */
33 i-cache-line-size = <32>;
[all …]
Dglacier.dts4 * Copyright 2008-2010 DENX Software Engineering, Stefan Roese <sr@denx.de>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
30 #address-cells = <1>;
31 #size-cells = <0>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
39 i-cache-line-size = <32>;
[all …]
Dobs600.dts8 * Copyright 2007-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
15 /dts-v1/;
18 #address-cells = <1>;
19 #size-cells = <1>;
22 dcr-parent = <&{/cpus/cpu@0}>;
32 #address-cells = <1>;
33 #size-cells = <0>;
39 clock-frequency = <0>; /* Filled in by U-Boot */
40 timebase-frequency = <0>; /* Filled in by U-Boot */
41 i-cache-line-size = <32>;
[all …]
/kernel/linux/linux-6.6/drivers/net/pcs/
Dpcs-xpcs-nxp.c1 // SPDX-License-Identifier: GPL-2.0
4 #include <linux/pcs/pcs-xpcs.h>
5 #include "pcs-xpcs.h"
68 * polarity inverted by default (PLUS is MINUS, MINUS is PLUS). To obtain
69 * normal non-inverted behavior, the TX lane polarity must be inverted in the
131 /* Program RX PLL feedback divider and reference divider for correct in nxp_sja1110_pma_config()
152 /* Enable TX and RX PLLs and circuits. in nxp_sja1110_pma_config()
168 /* Program continuous-time linear equalizer (CTLE) settings. */ in nxp_sja1110_pma_config()
/kernel/linux/linux-5.10/sound/drivers/
Dportman2x4.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) by Levent Guendogdu <levon@feature-it.com>
9 * - cleanup and rewrite
11 * - source code cleanup
13 * - fixed compilation problem with alsa 1.0.6a (removed MODULE_CLASSES,
17 * - added 2.6 kernel support
19 …* - added parport_unregister_driver to the startup routine if the driver fails to detect a po…
20 * - added support for all 4 output ports in portman_putmidi
22 * - added checks for opened input device in interrupt handler
24 * - ported from alsa 0.5 to 1.0
[all …]
/kernel/linux/linux-6.6/sound/drivers/
Dportman2x4.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) by Levent Guendogdu <levon@feature-it.com>
9 * - cleanup and rewrite
11 * - source code cleanup
13 * - fixed compilation problem with alsa 1.0.6a (removed MODULE_CLASSES,
17 * - added 2.6 kernel support
19 …* - added parport_unregister_driver to the startup routine if the driver fails to detect a po…
20 * - added support for all 4 output ports in portman_putmidi
22 * - added checks for opened input device in interrupt handler
24 * - ported from alsa 0.5 to 1.0
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/microchip/
Dat91-kizbox2-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * at91-kizbox2_common.dtsi - Device Tree Include file for
6 * Copyright (C) 2014-2018 Overkiz SAS
17 stdout-path = &dbgu;
26 clock-frequency = <32768>;
30 clock-frequency = <12000000>;
34 gpio-keys {
35 compatible = "gpio-keys";
37 button-prog {
41 wakeup-source;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dat91-kizbox2-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * at91-kizbox2_common.dtsi - Device Tree Include file for
6 * Copyright (C) 2014-2018 Overkiz SAS
17 stdout-path = &dbgu;
26 clock-frequency = <32768>;
30 clock-frequency = <12000000>;
35 compatible = "gpio-keys";
36 #address-cells = <1>;
37 #size-cells = <0>;
43 wakeup-source;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/input/rmi4/
Drmi_spi.txt10 - compatible: syna,rmi4-spi
11 - reg: Chip select address for the device
12 - #address-cells: Set to 1 to indicate that the function child nodes
14 - #size-cells: Set to 0 to indicate that the function child nodes do not
18 - interrupts: interrupt which the rmi device is connected to.
19 See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
21 - spi-rx-delay-us: microsecond delay after a read transfer.
22 - spi-tx-delay-us: microsecond delay after a write transfer.
33 rmi4-spi-dev@0 {
34 compatible = "syna,rmi4-spi";
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/input/touchscreen/
Dazoteq,iqs7211.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
13 The Azoteq IQS7210A, IQS7211A and IQS7211E trackpad and touchscreen control-
14 lers employ projected-capacitance sensing and can track two contacts.
21 - azoteq,iqs7210a
22 - azoteq,iqs7211a
23 - azoteq,iqs7211e
28 irq-gpios:
[all …]

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