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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/
Dbrcm,iproc-pcie.txt1 * Broadcom iProc PCIe controller with the platform bus interface
4 - compatible:
5 "brcm,iproc-pcie" for the first generation of PAXB based controller,
7 "brcm,iproc-pcie-paxb-v2" for the second generation of PAXB-based
9 "brcm,iproc-pcie-paxc" for the first generation of PAXC based
11 "brcm,iproc-pcie-paxc-v2" for the second generation of PAXC based
13 PAXB-based root complex is used for external endpoint devices. PAXC-based
15 - reg: base address and length of the PCIe controller I/O register space
16 - #interrupt-cells: set to <1>
17 - interrupt-map-mask and interrupt-map, standard PCI properties to define the
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/
Dbrcm,iproc-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,iproc-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom iProc PCIe controller with the platform bus interface
10 - Ray Jui <ray.jui@broadcom.com>
11 - Scott Branden <scott.branden@broadcom.com>
14 - $ref: /schemas/pci/pci-bus.yaml#
19 - enum:
22 - brcm,iproc-pcie
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/kernel/linux/linux-5.10/drivers/pci/controller/
Dpcie-iproc-msi.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/msi.h>
14 #include "pcie-iproc.h"
34 /* Size of each MSI address region */
52 * iProc MSI group
54 * One MSI group is allocated per GIC interrupt, serviced by one iProc MSI
57 * @msi: pointer to iProc MSI data
62 struct iproc_msi *msi; member
68 * iProc event queue based MSI
70 * Only meant to be used on platforms without MSI support integrated into the
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Dpcie-iproc.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2014-2015 Broadcom Corporation
10 * iProc PCIe interface type
27 * iProc PCIe outbound mapping
29 * the iProc PCIe core
38 * iProc PCIe inbound mapping
50 * iProc PCIe device
53 * @type: iProc PCIe interface type
60 * @iproc_cfg_read: indicates the iProc config read function should be used
76 * @need_msi_steer: indicates additional configuration of the iProc PCIe
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DKconfig1 # SPDX-License-Identifier: GPL-2.0
50 bool "Renesas R-Car Gen2 Internal PCI controller"
54 Say Y here if you want internal PCI support on R-Car Gen2 SoC.
56 built-in EHCI/OHCI host controller present on each one.
59 bool "Renesas R-Car PCIe controller"
64 Say Y here if you want PCIe controller support on R-Car SoCs.
68 bool "Renesas R-Car PCIe host controller"
73 Say Y here if you want PCIe controller support on R-Car SoCs in host
77 bool "Renesas R-Car PCIe endpoint controller"
81 Say Y here if you want PCIe controller support on R-Car SoCs in
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PCIE_CADENCE) += cadence/
3 obj-$(CONFIG_PCI_FTPCI100) += pci-ftpci100.o
4 obj-$(CONFIG_PCI_HYPERV) += pci-hyperv.o
5 obj-$(CONFIG_PCI_HYPERV_INTERFACE) += pci-hyperv-intf.o
6 obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
7 obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o
8 obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
9 obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
10 obj-$(CONFIG_PCIE_RCAR_HOST) += pcie-rcar.o pcie-rcar-host.o
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Dpcie-iproc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
9 #include <linux/msi.h>
16 #include <linux/irqchip/arm-gic-v3.h>
24 #include "pcie-iproc.h"
99 * iProc PCIe outbound mapping controller specific parameters
146 * iProc PCIe inbound mapping type
160 * iProc PCIe inbound mapping controller specific parameters
169 * @imap_addr_offset: register offset between the upper and lower 32-bit
239 * iProc PCIe host registers
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/kernel/linux/linux-6.6/drivers/pci/controller/
Dpcie-iproc-msi.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/msi.h>
14 #include "pcie-iproc.h"
34 /* Size of each MSI address region */
52 * struct iproc_msi_grp - iProc MSI group
54 * One MSI group is allocated per GIC interrupt, serviced by one iProc MSI
57 * @msi: pointer to iProc MSI data
62 struct iproc_msi *msi; member
68 * struct iproc_msi - iProc event queue based MSI
70 * Only meant to be used on platforms without MSI support integrated into the
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Dpcie-iproc.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2014-2015 Broadcom Corporation
10 * enum iproc_pcie_type - iProc PCIe interface type
11 * @IPROC_PCIE_PAXB_BCMA: BCMA-based host controllers
12 * @IPROC_PCIE_PAXB: PAXB-based host controllers for
14 * @IPROC_PCIE_PAXB_V2: PAXB-based host controllers for Stingray SoCs
15 * @IPROC_PCIE_PAXC: PAXC-based host controllers
16 * @IPROC_PCIE_PAXC_V2: PAXC-based host controllers (second generation)
33 * struct iproc_pcie_ob - iProc PCIe outbound mapping
35 * the iProc PCIe core
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DKconfig1 # SPDX-License-Identifier: GPL-2.0
25 tristate "Altera PCIe MSI feature"
29 Say Y here if you want PCIe MSI support for the Altera FPGA.
30 This MSI driver supports Altera MSI to GIC controller IP.
45 system-on-chips, like the Apple M1. This is required for the USB
46 type-A ports, Ethernet, Wi-Fi, and Bluetooth.
68 This enables the iProc PCIe core controller support for Broadcom's
69 iProc family of SoCs. An appropriate bus interface driver needs
73 tristate "Broadcom iProc PCIe platform bus driver"
79 Say Y here if you want to use the Broadcom iProc PCIe controller
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Dpcie-iproc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
9 #include <linux/pci-ecam.h>
10 #include <linux/msi.h>
17 #include <linux/irqchip/arm-gic-v3.h>
24 #include "pcie-iproc.h"
91 * struct iproc_pcie_ob_map - iProc PCIe outbound mapping controller-specific
138 * enum iproc_pcie_ib_map_type - iProc PCIe inbound mapping type
150 * struct iproc_pcie_ib_map - iProc PCIe inbound mapping controller-specific
159 * @imap_addr_offset: register offset between the upper and lower 32-bit
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PCIE_CADENCE) += cadence/
3 obj-$(CONFIG_PCI_FTPCI100) += pci-ftpci100.o
4 obj-$(CONFIG_PCI_IXP4XX) += pci-ixp4xx.o
5 obj-$(CONFIG_PCI_HYPERV) += pci-hyperv.o
6 obj-$(CONFIG_PCI_HYPERV_INTERFACE) += pci-hyperv-intf.o
7 obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
8 obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o
9 obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
10 obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
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/kernel/linux/linux-6.6/arch/arm64/boot/dts/broadcom/northstar2/
Dns2.dtsi35 #include <dt-bindings/interrupt-controller/arm-gic.h>
36 #include <dt-bindings/clock/bcm-ns2.h>
40 interrupt-parent = <&gic>;
41 #address-cells = <2>;
42 #size-cells = <2>;
45 #address-cells = <2>;
46 #size-cells = <0>;
50 compatible = "arm,cortex-a57";
52 enable-method = "psci";
53 next-level-cache = <&CLUSTER0_L2>;
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/broadcom/northstar2/
Dns2.dtsi35 #include <dt-bindings/interrupt-controller/arm-gic.h>
36 #include <dt-bindings/clock/bcm-ns2.h>
40 interrupt-parent = <&gic>;
41 #address-cells = <2>;
42 #size-cells = <2>;
45 #address-cells = <2>;
46 #size-cells = <0>;
50 compatible = "arm,cortex-a57";
52 enable-method = "psci";
53 next-level-cache = <&CLUSTER0_L2>;
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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dbcm-hr2.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
39 interrupt-parent = <&gic>;
40 #address-cells = <1>;
41 #size-cells = <1>;
44 #address-cells = <1>;
45 #size-cells = <0>;
49 compatible = "arm,cortex-a9";
50 next-level-cache = <&L2>;
56 compatible = "arm,cortex-a9-pmu";
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Dbcm-nsp.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
35 #include <dt-bindings/clock/bcm-nsp.h>
38 #address-cells = <1>;
39 #size-cells = <1>;
42 interrupt-parent = <&gic>;
53 #address-cells = <1>;
54 #size-cells = <0>;
58 compatible = "arm,cortex-a9";
59 next-level-cache = <&L2>;
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Dbcm-cygnus.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
35 #include <dt-bindings/clock/bcm-cygnus.h>
38 #address-cells = <1>;
39 #size-cells = <1>;
42 interrupt-parent = <&gic>;
54 #address-cells = <1>;
55 #size-cells = <0>;
59 compatible = "arm,cortex-a9";
60 next-level-cache = <&L2>;
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/kernel/linux/linux-6.6/arch/arm/boot/dts/broadcom/
Dbcm-hr2.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
39 interrupt-parent = <&gic>;
40 #address-cells = <1>;
41 #size-cells = <1>;
44 #address-cells = <1>;
45 #size-cells = <0>;
49 compatible = "arm,cortex-a9";
50 next-level-cache = <&L2>;
56 compatible = "arm,cortex-a9-pmu";
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Dbcm-nsp.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
35 #include <dt-bindings/clock/bcm-nsp.h>
38 #address-cells = <1>;
39 #size-cells = <1>;
42 interrupt-parent = <&gic>;
53 #address-cells = <1>;
54 #size-cells = <0>;
58 compatible = "arm,cortex-a9";
59 next-level-cache = <&L2>;
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Dbcm-cygnus.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
35 #include <dt-bindings/clock/bcm-cygnus.h>
38 #address-cells = <1>;
39 #size-cells = <1>;
42 interrupt-parent = <&gic>;
54 #address-cells = <1>;
55 #size-cells = <0>;
59 compatible = "arm,cortex-a9";
60 next-level-cache = <&L2>;
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/kernel/linux/linux-6.6/arch/arm64/boot/dts/broadcom/stingray/
Dstingray-fs4.dtsi4 * Copyright(c) 2016-2017 Broadcom. All rights reserved.
34 compatible = "simple-bus";
35 #address-cells = <1>;
36 #size-cells = <1>;
40 compatible = "brcm,iproc-flexrm-mbox";
42 msi-parent = <&gic_its 0x4100>;
43 #mbox-cells = <3>;
44 dma-coherent;
48 compatible = "brcm,iproc-flexrm-mbox";
50 dma-coherent;
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Dstingray.dtsi4 * Copyright(c) 2015-2017 Broadcom. All rights reserved.
33 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 interrupt-parent = <&gic>;
38 #address-cells = <2>;
39 #size-cells = <2>;
42 #address-cells = <2>;
43 #size-cells = <0>;
47 compatible = "arm,cortex-a72";
49 enable-method = "psci";
50 next-level-cache = <&CLUSTER0_L2>;
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/broadcom/stingray/
Dstingray-fs4.dtsi4 * Copyright(c) 2016-2017 Broadcom. All rights reserved.
34 compatible = "simple-bus";
35 #address-cells = <1>;
36 #size-cells = <1>;
40 compatible = "brcm,iproc-flexrm-mbox";
42 msi-parent = <&gic_its 0x4100>;
43 #mbox-cells = <3>;
44 dma-coherent;
48 compatible = "brcm,iproc-flexrm-mbox";
50 dma-coherent;
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mailbox/
Dbrcm,iproc-flexrm-mbox.txt6 FlexRM driver will create a mailbox-controller instance for given FlexRM
10 --------------------
11 - compatible: Should be "brcm,iproc-flexrm-mbox"
12 - reg: Specifies base physical address and size of the FlexRM
14 - msi-parent: Phandles (and potential Device IDs) to MSI controllers
16 interrupts) to CPU. There is one MSI for each FlexRM ring.
17 Refer devicetree/bindings/interrupt-controller/msi.txt
18 - #mbox-cells: Specifies the number of cells needed to encode a mailbox
23 The 2nd cell contains MSI completion threshold. This is the
25 one MSI interrupt to CPU.
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mailbox/
Dbrcm,iproc-flexrm-mbox.txt6 FlexRM driver will create a mailbox-controller instance for given FlexRM
10 --------------------
11 - compatible: Should be "brcm,iproc-flexrm-mbox"
12 - reg: Specifies base physical address and size of the FlexRM
14 - msi-parent: Phandles (and potential Device IDs) to MSI controllers
16 interrupts) to CPU. There is one MSI for each FlexRM ring.
17 Refer devicetree/bindings/interrupt-controller/msi.txt
18 - #mbox-cells: Specifies the number of cells needed to encode a mailbox
23 The 2nd cell contains MSI completion threshold. This is the
25 one MSI interrupt to CPU.
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