| /kernel/linux/linux-6.6/drivers/pci/controller/cadence/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 menu "Cadence-based PCIe controllers"
25 bool "Cadence platform PCIe controller (host mode)"
30 Say Y here if you want to support the Cadence PCIe platform controller in
31 host mode. This PCIe controller may be embedded into many different
35 bool "Cadence platform PCIe controller (endpoint mode)"
41 Say Y here if you want to support the Cadence PCIe platform controller in
42 endpoint mode. This PCIe controller may be embedded into many
49 bool "TI J721E PCIe controller (host mode)"
54 Say Y here if you want to support the TI J721E PCIe platform
[all …]
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| D | pci-j721e.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * pci-j721e - PCIe controller driver for TI's J721E SoCs
5 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
10 #include <linux/clk-provider.h>
25 #include "pcie-cadence.h"
27 #define cdns_pcie_to_rc(p) container_of(p, struct cdns_pcie_rc, pcie)
80 static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset) in j721e_pcie_user_readl() argument
82 return readl(pcie->user_cfg_base + offset); in j721e_pcie_user_readl()
85 static inline void j721e_pcie_user_writel(struct j721e_pcie *pcie, u32 offset, in j721e_pcie_user_writel() argument
88 writel(value, pcie->user_cfg_base + offset); in j721e_pcie_user_writel()
[all …]
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| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PCIE_CADENCE) += pcie-cadence.o
3 obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host.o
4 obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep.o
5 obj-$(CONFIG_PCIE_CADENCE_PLAT) += pcie-cadence-plat.o
6 obj-$(CONFIG_PCI_J721E) += pci-j721e.o
|
| /kernel/linux/linux-5.10/drivers/pci/controller/cadence/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 menu "Cadence PCIe controllers support"
25 bool "Cadence PCIe platform host controller"
30 Say Y here if you want to support the Cadence PCIe platform controller in
31 host mode. This PCIe controller may be embedded into many different
35 bool "Cadence PCIe platform endpoint controller"
41 Say Y here if you want to support the Cadence PCIe platform controller in
42 endpoint mode. This PCIe controller may be embedded into many
49 bool "TI J721E PCIe platform host controller"
54 Say Y here if you want to support the TI J721E PCIe platform
[all …]
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| D | pci-j721e.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * pci-j721e - PCIe controller driver for TI's J721E SoCs
5 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
22 #include "pcie-cadence.h"
74 static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset) in j721e_pcie_user_readl() argument
76 return readl(pcie->user_cfg_base + offset); in j721e_pcie_user_readl()
79 static inline void j721e_pcie_user_writel(struct j721e_pcie *pcie, u32 offset, in j721e_pcie_user_writel() argument
82 writel(value, pcie->user_cfg_base + offset); in j721e_pcie_user_writel()
85 static inline u32 j721e_pcie_intd_readl(struct j721e_pcie *pcie, u32 offset) in j721e_pcie_intd_readl() argument
87 return readl(pcie->intd_cfg_base + offset); in j721e_pcie_intd_readl()
[all …]
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| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PCIE_CADENCE) += pcie-cadence.o
3 obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host.o
4 obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep.o
5 obj-$(CONFIG_PCIE_CADENCE_PLAT) += pcie-cadence-plat.o
6 obj-$(CONFIG_PCI_J721E) += pci-j721e.o
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/ |
| D | ti,j721e-pci-host.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: TI J721E PCI Host (PCIe Wrapper)
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 - $ref: cdns-pcie-host.yaml#
19 - const: ti,j721e-pcie-host
20 - description: PCIe controller in AM64
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | ti,j721e-pci-host.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: TI J721E PCI Host (PCIe Wrapper)
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 - $ref: "cdns-pcie-host.yaml#"
19 - ti,j721e-pcie-host
24 reg-names:
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/ti/ |
| D | k3-j721e-main.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for J721E SoC Family Main Domain peripherals
5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/mux/mux.h>
9 #include <dt-bindings/mux/ti-serdes.h>
12 cmn_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
[all …]
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| D | k3-j721e-common-proc-board.dts | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
8 #include "k3-j721e-som-p0.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/net/ti-dp83867.h>
15 stdout-path = "serial2:115200n8";
19 gpio_keys: gpio-keys {
20 compatible = "gpio-keys";
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/ |
| D | ti,k3-am654-cpts.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,k3-am654-cpts.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: The TI AM654x/J721E Common Platform Time Sync (CPTS) module Device Tree Bindings
10 - Grygorii Strashko <grygorii.strashko@ti.com>
11 - Sekhar Nori <nsekhar@ti.com>
14 The TI AM654x/J721E CPTS module is used to facilitate host control of time
17 - selection of multiple external clock sources
18 - Software control of time sync events via interrupt or polling
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/ |
| D | ti,k3-am654-cpts.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,k3-am654-cpts.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: The TI AM654x/J721E Common Platform Time Sync (CPTS) module
10 - Grygorii Strashko <grygorii.strashko@ti.com>
11 - Sekhar Nori <nsekhar@ti.com>
14 The TI AM654x/J721E CPTS module is used to facilitate host control of time
17 - selection of multiple external clock sources
18 - Software control of time sync events via interrupt or polling
[all …]
|
| /kernel/linux/linux-5.10/drivers/usb/cdns3/ |
| D | Kconfig | 2 tristate "Cadence USB3 Dual-Role Controller"
7 Say Y here if your system has a Cadence USB3 dual-role controller.
8 It supports: dual-role switch, Host-only, and Peripheral-only.
20 Cadence USBSS-DEV driver.
26 bool "Cadence USB3 host controller"
29 Say Y here to enable host controller functionality of the
32 Host controller is compliant with XHCI so it will use
36 tristate "Cadence USB3 support on PCIe-based platforms"
40 If you're using the USBSS Core IP with a PCIe, please say
44 be dynamically linked and module will be called cdns3-pci.ko
[all …]
|
| /kernel/linux/linux-6.6/drivers/phy/ti/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
34 PCIe.
37 tristate "TI J721E WIZ (SERDES Wrapper) support"
46 This option enables support for WIZ module present in TI's J721E
60 additional register to power on USB3 PHY/SATA PHY/PCIE PHY
105 in host mode, low speed.
|
| /kernel/linux/linux-5.10/drivers/phy/ti/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
34 PCIe.
37 tristate "TI J721E WIZ (SERDES Wrapper) support"
46 This option enables support for WIZ module present in TI's J721E
60 additional register to power on USB3 PHY/SATA PHY/PCIE PHY
105 in host mode, low speed.
|
| /kernel/linux/linux-6.6/drivers/usb/cdns3/ |
| D | Kconfig | 8 dual-role controller.
9 It supports: dual-role switch, Host-only, and Peripheral-only.
17 tristate "Cadence USB3 Dual-Role Controller"
20 Say Y here if your system has a Cadence USB3 dual-role controller.
21 It supports: dual-role switch, Host-only, and Peripheral-only.
34 Cadence USBSS-DEV driver.
40 bool "Cadence USB3 host controller"
44 Say Y here to enable host controller functionality of the
47 Host controller is compliant with XHCI so it will use
51 tristate "Cadence USB3 support on PCIe-based platforms"
[all …]
|
| /kernel/linux/linux-6.6/arch/arm64/boot/dts/ti/ |
| D | k3-j7200-main.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
9 serdes_refclk: serdes-refclk {
10 #clock-cells = <0>;
11 compatible = "fixed-clock";
17 compatible = "mmio-sram";
19 #address-cells = <1>;
20 #size-cells = <1>;
23 atf-sram@0 {
28 scm_conf: scm-conf@100000 {
[all …]
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| D | k3-j721e-main.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for J721E SoC Family Main Domain peripherals
5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/phy/phy-ti.h>
9 #include <dt-bindings/mux/mux.h>
11 #include "k3-serdes.h"
14 cmn_refclk: clock-cmnrefclk {
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
[all …]
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| D | k3-j721s2-main.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
[all …]
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| D | k3-am64-main.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
[all …]
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| D | k3-j721e-common-proc-board.dts | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
10 #include "k3-j721e-som-p0.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/net/ti-dp83867.h>
14 #include <dt-bindings/phy/phy-cadence.h>
17 compatible = "ti,j721e-evm", "ti,j721e";
18 model = "Texas Instruments J721e EVM";
[all …]
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| D | k3-j721e-sk.dts | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
5 * J721E SK URL: https://www.ti.com/tool/SK-TDA4VM
8 /dts-v1/;
10 #include "k3-j721e.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/net/ti-dp83867.h>
16 compatible = "ti,j721e-sk", "ti,j721e";
17 model = "Texas Instruments J721E SK";
[all …]
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| D | k3-j721e-beagleboneai64.dts | 1 // SPDX-License-Identifier: GPL-2.0
3 * https://beagleboard.org/ai-64
4 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
9 /dts-v1/;
11 #include "k3-j721e.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/leds/common.h>
15 #include <dt-bindings/net/ti-dp83867.h>
16 #include <dt-bindings/phy/phy-cadence.h>
[all …]
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| /kernel/linux/linux-6.6/ |
| D | MAINTAINERS | 5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
[all …]
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| /kernel/linux/linux-5.10/ |
| D | MAINTAINERS | 9 -------------------------
30 ``diff -u`` to make the patch easy to merge. Be prepared to get your
40 See Documentation/process/coding-style.rst for guidance here.
46 See Documentation/process/submitting-patches.rst for details.
57 include a Signed-off-by: line. The current version of this
59 Documentation/process/submitting-patches.rst.
70 that the bug would present a short-term risk to other users if it
76 Documentation/admin-guide/security-bugs.rst for details.
81 ---------------------------------------------------
97 W: *Web-page* with status/info
[all …]
|