l2\-data\-latency (full) in projects: kernel

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Searched +full:l2 +full:- +full:data +full:- +full:latency (Results 1 – 25 of 358) sorted by relevance

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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
D	baikal,bt1-l2-ctl.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/memory-controllers/baikal,bt1-l2-ctl.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: Baikal-T1 L2-cache Control Block 11 - Serge Semin <fancer.lancer@gmail.com> 14 By means of the System Controller Baikal-T1 SoC exposes a few settings to 15 tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible 16 to change the Tag, Data and Way-select RAM access latencies. Baikal-T1 17 L2-cache controller block is responsible for the tuning. Its DT node is [all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/cache/
D	baikal,bt1-l2-ctl.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/cache/baikal,bt1-l2-ctl.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: Baikal-T1 L2-cache Control Block 11 - Serge Semin <fancer.lancer@gmail.com> 14 By means of the System Controller Baikal-T1 SoC exposes a few settings to 15 tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible 16 to change the Tag, Data and Way-select RAM access latencies. Baikal-T1 17 L2-cache controller block is responsible for the tuning. Its DT node is [all …]
D	l2c2x0.yaml	1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: ARM L2 Cache Controller 10 - Rob Herring <robh@kernel.org> 15 implementations of the L2 cache controller have compatible programming 16 models (Note 1). Some of the properties that are just prefixed "cache-*" are 21 Note 1: The description in this document doesn't apply to integrated L2 22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These 23 integrated L2 controllers are assumed to be all preconfigured by [all …]
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/icelakex/
D	memory.json	19 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple… 26 …s when the latency from first dispatch to completion is greater than 128 cycles. Reported latency… 31 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple… 38 …ds when the latency from first dispatch to completion is greater than 16 cycles. Reported latency… 43 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple… 50 …s when the latency from first dispatch to completion is greater than 256 cycles. Reported latency… 55 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple… 62 …ds when the latency from first dispatch to completion is greater than 32 cycles. Reported latency… 67 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple… 74 …ds when the latency from first dispatch to completion is greater than 4 cycles. Reported latency … [all …]
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/sapphirerapids/
D	memory.json	35 …"BriefDescription": "Execution stalls while L2 cache miss demand cacheable load request is outstan… 39 …"PublicDescription": "Execution stalls while L2 cache miss demand cacheable load request is outsta… 53 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple… 60 …s when the latency from first dispatch to completion is greater than 128 cycles. Reported latency… 65 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple… 72 …ds when the latency from first dispatch to completion is greater than 16 cycles. Reported latency… 77 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple… 84 …s when the latency from first dispatch to completion is greater than 256 cycles. Reported latency… 89 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple… 96 …ds when the latency from first dispatch to completion is greater than 32 cycles. Reported latency… [all …]
/kernel/linux/linux-5.10/drivers/memory/
D	bt1-l2-ctl.c	1 // SPDX-License-Identifier: GPL-2.0-only 8 * Baikal-T1 CM2 L2-cache Control Block driver. 38 * struct l2_ctl - Baikal-T1 L2 Control block private data. 40 * @sys_regs: Baikal-T1 System Controller registers map. 49 * enum l2_ctl_stall - Baikal-T1 L2-cache-RAM stall identifier. 50 * @L2_WSSTALL: Way-select latency. 51 * @L2_TAGSTALL: Tag latency. 52 * @L2_DATASTALL: Data latency. 61 * struct l2_ctl_device_attribute - Baikal-T1 L2-cache device attribute. 63 * @id: L2-cache stall field identifier. [all …]
/kernel/linux/linux-6.6/drivers/memory/
D	bt1-l2-ctl.c	1 // SPDX-License-Identifier: GPL-2.0-only 8 * Baikal-T1 CM2 L2-cache Control Block driver. 38 * struct l2_ctl - Baikal-T1 L2 Control block private data. 40 * @sys_regs: Baikal-T1 System Controller registers map. 49 * enum l2_ctl_stall - Baikal-T1 L2-cache-RAM stall identifier. 50 * @L2_WSSTALL: Way-select latency. 51 * @L2_TAGSTALL: Tag latency. 52 * @L2_DATASTALL: Data latency. 61 * struct l2_ctl_device_attribute - Baikal-T1 L2-cache device attribute. 63 * @id: L2-cache stall field identifier. [all …]
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/alderlake/
D	cache.json	11 "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.", 14 …": "Counts L1D data line replacements including opportunistic replacements, and replacements that … 49 …scription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.", 52 …nts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand re… 61 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti… 77 "BriefDescription": "L2 cache lines filling L2", 80 …"PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover … 86 …"BriefDescription": "Cache lines that have been L2 hardware prefetched but not used by demand acce… 89 …ines that have been prefetched by the L2 hardware prefetcher but not used by demand access when ev… 95 "BriefDescription": "All accesses to L2 cache [This event is alias to L2_RQSTS.REFERENCES]", [all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/
D	l2c2x0.yaml	1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: ARM L2 Cache Controller 10 - Rob Herring <robh@kernel.org> 15 implementations of the L2 cache controller have compatible programming 16 models (Note 1). Some of the properties that are just prefixed "cache-*" are 21 Note 1: The description in this document doesn't apply to integrated L2 22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These 23 integrated L2 controllers are assumed to be all preconfigured by [all …]
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/alderlaken/
D	cache.json	6 …the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a p… 14 …the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a p… 19 …talled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", 22 …che or translation lookaside buffer (TLB) miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", 27 …the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM).", 30 …nstruction cache or translation lookaside buffer (TLB) miss which hit in DRAM or MMIO (non-DRAM).", 35 … of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.", 38 …due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache.", 51 … the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", 58 …ber of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", [all …]
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/powerpc/power9/
D	metrics.json	50 …the NTF instruction was a load that missed the L1 and was waiting for the data to return from the … 56 …"BriefDescription": "Finish stall because the NTF instruction was a multi-cycle instruction issued… 62 "BriefDescription": "Stalls due to short latency decimal floating ops.", 63 "MetricExpr": "dfu_stall_cpi - dflong_stall_cpi", 75 "MetricExpr": "dmiss_non_local_stall_cpi - dmiss_remote_stall_cpi", 80 …iefDescription": "Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3)", 86 …"BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 with a confl… 92 …"BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 without conf… 93 "MetricExpr": "dmiss_l2l3_stall_cpi - dmiss_l2l3_conflict_stall_cpi", 98 "BriefDescription": "Completion stall by Dcache miss which resolved in L2/L3", [all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/powerpc/power9/
D	metrics.json	50 …the NTF instruction was a load that missed the L1 and was waiting for the data to return from the … 56 …"BriefDescription": "Finish stall because the NTF instruction was a multi-cycle instruction issued… 62 "BriefDescription": "Stalls due to short latency decimal floating ops.", 63 "MetricExpr": "dfu_stall_cpi - dflong_stall_cpi", 75 "MetricExpr": "dmiss_non_local_stall_cpi - dmiss_remote_stall_cpi", 80 …iefDescription": "Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3)", 86 …"BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 with a confl… 92 …"BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 without conf… 93 "MetricExpr": "dmiss_l2l3_stall_cpi - dmiss_l2l3_conflict_stall_cpi", 98 "BriefDescription": "Completion stall by Dcache miss which resolved in L2/L3", [all …]
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/ivytown/
D	memory.json	10 "BriefDescription": "Loads with latency value being above 128", 16 "PublicDescription": "Loads with latency value being above 128.", 21 "BriefDescription": "Loads with latency value being above 16", 27 "PublicDescription": "Loads with latency value being above 16.", 32 "BriefDescription": "Loads with latency value being above 256", 38 "PublicDescription": "Loads with latency value being above 256.", 43 "BriefDescription": "Loads with latency value being above 32", 49 "PublicDescription": "Loads with latency value being above 32.", 54 "BriefDescription": "Loads with latency value being above 4", 60 "PublicDescription": "Loads with latency value being above 4.", [all …]
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/jaketown/
D	memory.json	6 …lears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores… 11 "BriefDescription": "Loads with latency value being above 128.", 21 "BriefDescription": "Loads with latency value being above 16.", 31 "BriefDescription": "Loads with latency value being above 256.", 41 "BriefDescription": "Loads with latency value being above 32.", 51 "BriefDescription": "Loads with latency value being above 4 .", 61 "BriefDescription": "Loads with latency value being above 512.", 71 "BriefDescription": "Loads with latency value being above 64.", 81 "BriefDescription": "Loads with latency value being above 8.", 91 …le stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).", [all …]
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/meteorlake/
D	cache.json	11 "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.", 14 …": "Counts L1D data line replacements including opportunistic replacements, and replacements that … 40 …scription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.", 43 …nts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand re… 52 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti… 68 "BriefDescription": "L2 cache lines filling L2", 71 …"PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover … 77 …riefDescription": "Modified cache lines that are evicted by L2 cache when triggered by an L2 cache… 80 …scription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache… 86 …"BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered… [all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/jaketown/
D	memory.json	3 …lears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores… 21 "BriefDescription": "Loads with latency value being above 4 .", 34 "BriefDescription": "Loads with latency value being above 8.", 47 "BriefDescription": "Loads with latency value being above 16.", 60 "BriefDescription": "Loads with latency value being above 32.", 73 "BriefDescription": "Loads with latency value being above 64.", 86 "BriefDescription": "Loads with latency value being above 128.", 99 "BriefDescription": "Loads with latency value being above 256.", 112 "BriefDescription": "Loads with latency value being above 512.", 123 …le stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).", [all …]
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/amdzen4/
D	cache.json	5 …iption": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for load-store all… 11 …"BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for har… 17 …"BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for all… 23 "BriefDescription": "Demand data cache fills from local L2 cache.", 29 …"BriefDescription": "Demand data cache fills from L3 cache or different L2 cache in the same CCX.", 35 …"BriefDescription": "Demand data cache fills from cache of another CCX when the address was in the… 41 "BriefDescription": "Demand data cache fills from either DRAM or MMIO in the same NUMA node.", 47 …"BriefDescription": "Demand data cache fills from cache of another CCX when the address was in a d… 53 …"BriefDescription": "Demand data cache fills from either DRAM or MMIO in a different NUMA node (sa… 59 "BriefDescription": "Demand data cache fills from extension memory.", [all …]
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/graniterapids/
D	cache.json	3 "BriefDescription": "L2 code requests", 6 "PublicDescription": "Counts the total number of L2 code requests.", 11 "BriefDescription": "Demand Data Read access L2 cache", 14 …emand Data Read requests accessing the L2 cache. These requests may hit or miss L2 cache. True-mis… 19 …"BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetche… 22 …-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include da… 27 …"BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetch… 30 …-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and …
D	memory.json	3 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple… 10 …s when the latency from first dispatch to completion is greater than 128 cycles. Reported latency… 15 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple… 22 …ds when the latency from first dispatch to completion is greater than 16 cycles. Reported latency… 27 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple… 34 …s when the latency from first dispatch to completion is greater than 256 cycles. Reported latency… 39 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple… 46 …ds when the latency from first dispatch to completion is greater than 32 cycles. Reported latency… 51 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple… 58 …ds when the latency from first dispatch to completion is greater than 4 cycles. Reported latency … [all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/ivytown/
D	memory.json	3 "PublicDescription": "Speculative cache-line split load uops dispatched to L1D.", 13 "PublicDescription": "Speculative cache-line split Store-address uops dispatched to L1D.", 33 "PublicDescription": "Loads with latency value being above 4.", 41 "BriefDescription": "Loads with latency value being above 4", 47 "PublicDescription": "Loads with latency value being above 8.", 55 "BriefDescription": "Loads with latency value being above 8", 61 "PublicDescription": "Loads with latency value being above 16.", 69 "BriefDescription": "Loads with latency value being above 16", 75 "PublicDescription": "Loads with latency value being above 32.", 83 "BriefDescription": "Loads with latency value being above 32", [all …]
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/skylakex/
D	memory.json	57 …"BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions a… 84 …f the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores… 89 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple… 96 …s when the latency from first dispatch to completion is greater than 128 cycles. Reported latency… 101 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple… 108 …ds when the latency from first dispatch to completion is greater than 16 cycles. Reported latency… 113 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple… 120 …s when the latency from first dispatch to completion is greater than 256 cycles. Reported latency… 125 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple… 132 …ds when the latency from first dispatch to completion is greater than 32 cycles. Reported latency… [all …]
/kernel/linux/linux-5.10/Documentation/x86/
D	resctrl_ui.rst	1 .. SPDX-License-Identifier: GPL-2.0 9 :Authors: - Fenghua Yu <fenghua.yu@intel.com> 10 - Tony Luck <tony.luck@intel.com> 11 - Vikas Shivappa <vikas.shivappa@intel.com> 23 CDP (Code and Data Prioritization) "cdp_l3", "cdp_l2" 31 # mount -t resctrl resctrl [-o cdp[,cdpl2][,mba_MBps]] /sys/fs/resctrl 36 Enable code/data prioritization in L3 cache allocations. 38 Enable code/data prioritization in L2 cache allocations. 43 L2 and L3 CDP are controlled separately. 47 pseudo-locking is a unique way of using cache control to "pin" or [all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
D	vf610.dtsi	`1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 9 next-level-cache = <&L2>; 13 L2: cache-controller@40006000 { label 14 compatible = "arm,pl310-cache"; 16 cache-unified; 17 cache-level = <2>; 18 arm,data-latency = <3 3 3>; 19 arm,tag-latency = <2 2 2>;`
/kernel/linux/linux-6.6/arch/arm/boot/dts/nxp/vf/
D	vf610.dtsi	`1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 8 next-level-cache = <&L2>; 12 L2: cache-controller@40006000 { label 13 compatible = "arm,pl310-cache"; 15 cache-unified; 16 cache-level = <2>; 17 arm,data-latency = <3 3 3>; 18 arm,tag-latency = <2 2 2>;`
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/amdzen1/
D	cache.json	5 …tch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheab… 15 …"BriefDescription": "The number of 64 byte instruction cache line was fulfilled from the L2 cache." 25 …fDescription": "The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB." 30 "BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs." 35 … instruction stream was being modified by another processor in an MP system - typically a highly u… 52 …l. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.", 58 …"IC line invalidated due to L2 invalidating probe (external or LS). The number of instruction cach… 64 …ting fill response. The number of instruction cache lines invalidated. A non-SMC event is CMC (cro… 75 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har… 81 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.", [all …]

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