| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/ |
| D | baikal,bt1-l2-ctl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/memory-controllers/baikal,bt1-l2-ctl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 L2-cache Control Block
11 - Serge Semin <fancer.lancer@gmail.com>
14 By means of the System Controller Baikal-T1 SoC exposes a few settings to
15 tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible
16 to change the Tag, Data and Way-select RAM access latencies. Baikal-T1
17 L2-cache controller block is responsible for the tuning. Its DT node is
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/cache/ |
| D | baikal,bt1-l2-ctl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/cache/baikal,bt1-l2-ctl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 L2-cache Control Block
11 - Serge Semin <fancer.lancer@gmail.com>
14 By means of the System Controller Baikal-T1 SoC exposes a few settings to
15 tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible
16 to change the Tag, Data and Way-select RAM access latencies. Baikal-T1
17 L2-cache controller block is responsible for the tuning. Its DT node is
[all …]
|
| D | l2c2x0.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM L2 Cache Controller
10 - Rob Herring <robh@kernel.org>
15 implementations of the L2 cache controller have compatible programming
16 models (Note 1). Some of the properties that are just prefixed "cache-*" are
21 Note 1: The description in this document doesn't apply to integrated L2
22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
23 integrated L2 controllers are assumed to be all preconfigured by
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/ |
| D | l2c2x0.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM L2 Cache Controller
10 - Rob Herring <robh@kernel.org>
15 implementations of the L2 cache controller have compatible programming
16 models (Note 1). Some of the properties that are just prefixed "cache-*" are
21 Note 1: The description in this document doesn't apply to integrated L2
22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
23 integrated L2 controllers are assumed to be all preconfigured by
[all …]
|
| /kernel/linux/linux-5.10/drivers/memory/ |
| D | bt1-l2-ctl.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * Baikal-T1 CM2 L2-cache Control Block driver.
38 * struct l2_ctl - Baikal-T1 L2 Control block private data.
40 * @sys_regs: Baikal-T1 System Controller registers map.
49 * enum l2_ctl_stall - Baikal-T1 L2-cache-RAM stall identifier.
50 * @L2_WSSTALL: Way-select latency.
51 * @L2_TAGSTALL: Tag latency.
52 * @L2_DATASTALL: Data latency.
61 * struct l2_ctl_device_attribute - Baikal-T1 L2-cache device attribute.
63 * @id: L2-cache stall field identifier.
[all …]
|
| /kernel/linux/linux-6.6/drivers/memory/ |
| D | bt1-l2-ctl.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * Baikal-T1 CM2 L2-cache Control Block driver.
38 * struct l2_ctl - Baikal-T1 L2 Control block private data.
40 * @sys_regs: Baikal-T1 System Controller registers map.
49 * enum l2_ctl_stall - Baikal-T1 L2-cache-RAM stall identifier.
50 * @L2_WSSTALL: Way-select latency.
51 * @L2_TAGSTALL: Tag latency.
52 * @L2_DATASTALL: Data latency.
61 * struct l2_ctl_device_attribute - Baikal-T1 L2-cache device attribute.
63 * @id: L2-cache stall field identifier.
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/amdzen3/ |
| D | cache.json | 5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | vf610.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 next-level-cache = <&L2>;
13 L2: cache-controller@40006000 { label
14 compatible = "arm,pl310-cache";
16 cache-unified;
17 cache-level = <2>;
18 arm,data-latency = <3 3 3>;
19 arm,tag-latency = <2 2 2>;
|
| D | arm-realview-pbx-a9.dts | 23 /dts-v1/;
24 #include "arm-realview-pbx.dtsi"
28 * This is the RealView Platform Baseboard Explore for Cortex-A9
31 model = "ARM RealView Platform Baseboard Explore for Cortex-A9";
35 #address-cells = <1>;
36 #size-cells = <0>;
37 enable-method = "arm,realview-smp";
39 cpu-map {
51 compatible = "arm,cortex-a9";
53 next-level-cache = <&L2>;
[all …]
|
| D | vexpress-v2p-ca9.dts | 1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A9 MPCore (V2P-CA9)
8 * HBI-0191B
11 /dts-v1/;
12 #include "vexpress-v2m.dtsi"
15 model = "V2P-CA9";
18 compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <1>;
21 #size-cells = <1>;
[all …]
|
| D | berlin2q.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
6 #include <dt-bindings/clock/berlin2q.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 model = "Marvell Armada 1500 pro (BG2-Q) SoC";
12 #address-cells = <1>;
13 #size-cells = <1>;
21 #address-cells = <1>;
22 #size-cells = <0>;
23 enable-method = "marvell,berlin-smp";
[all …]
|
| D | owl-s500.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright (c) 2016-2017 Andreas Färber
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/power/owl-s500-powergate.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
24 #address-cells = <1>;
25 #size-cells = <0>;
29 compatible = "arm,cortex-a9";
[all …]
|
| D | meson8b.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 #include <dt-bindings/clock/meson8-ddr-clkc.h>
8 #include <dt-bindings/clock/meson8b-clkc.h>
9 #include <dt-bindings/gpio/meson8b-gpio.h>
10 #include <dt-bindings/power/meson8-power.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
12 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a5";
[all …]
|
| /kernel/linux/linux-6.6/arch/arm/boot/dts/nxp/vf/ |
| D | vf610.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 next-level-cache = <&L2>;
12 L2: cache-controller@40006000 { label
13 compatible = "arm,pl310-cache";
15 cache-unified;
16 cache-level = <2>;
17 arm,data-latency = <3 3 3>;
18 arm,tag-latency = <2 2 2>;
|
| /kernel/linux/linux-6.6/tools/arch/x86/include/asm/ |
| D | amd-ibs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
4 * 55898 Rev 0.35 - Feb 5, 2021
7 #include "msr-index.h"
33 __u64 fetch_maxcnt:16,/* 0-15: instruction fetch max. count */
34 fetch_cnt:16, /* 16-31: instruction fetch count */
35 fetch_lat:16, /* 32-47: instruction fetch latency */
39 ic_miss:1, /* 51: i-cache miss */
41 l1tlb_pgsz:2, /* 53-54: i-cache L1TLB page size
43 l1tlb_miss:1, /* 55: i-cache fetch missed in L1TLB */
44 l2tlb_miss:1, /* 56: i-cache fetch missed in L2TLB */
[all …]
|
| /kernel/linux/linux-6.6/arch/x86/include/asm/ |
| D | amd-ibs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
4 * 55898 Rev 0.35 - Feb 5, 2021
7 #include <asm/msr-index.h>
33 __u64 fetch_maxcnt:16,/* 0-15: instruction fetch max. count */
34 fetch_cnt:16, /* 16-31: instruction fetch count */
35 fetch_lat:16, /* 32-47: instruction fetch latency */
39 ic_miss:1, /* 51: i-cache miss */
41 l1tlb_pgsz:2, /* 53-54: i-cache L1TLB page size
43 l1tlb_miss:1, /* 55: i-cache fetch missed in L1TLB */
44 l2tlb_miss:1, /* 56: i-cache fetch missed in L2TLB */
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/amdzen1/ |
| D | cache.json | 5 …tch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheab…
10 …Description": "The number of 32B fetch windows tried to read the L1 IC and missed in the full tag."
15 …"BriefDescription": "The number of 64 byte instruction cache line was fulfilled from the L2 cache."
25 …fDescription": "The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
30 "BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs."
35 … instruction stream was being modified by another processor in an MP system - typically a highly u…
52 …l. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.",
58 …"IC line invalidated due to L2 invalidating probe (external or LS). The number of instruction cach…
64 …ting fill response. The number of instruction cache lines invalidated. A non-SMC event is CMC (cro…
75 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/amdzen1/ |
| D | cache.json | 5 …tch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheab…
10 …Description": "The number of 32B fetch windows tried to read the L1 IC and missed in the full tag."
15 …"BriefDescription": "The number of 64 byte instruction cache line was fulfilled from the L2 cache."
25 …fDescription": "The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
30 "BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs."
35 … instruction stream was being modified by another processor in an MP system - typically a highly u…
52 …l. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.",
58 …"IC line invalidated due to L2 invalidating probe (external or LS). The number of instruction cach…
64 …ting fill response. The number of instruction cache lines invalidated. A non-SMC event is CMC (cro…
75 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/mm/ |
| D | cache-l2x0.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mm/cache-l2x0.c - L210/L220/L310 cache controller support
20 #include <asm/hardware/cache-l2x0.h>
21 #include <asm/hardware/cache-aurora-l2.h>
22 #include "cache-tauros3.h"
63 * override this if they are running non-secure.
77 * register be written due to a work-around, as platforms running
78 * in non-secure mode may not be able to access this register.
109 * Enable the L2 cache controller. This function must only be
119 l2x0_data->configure(base); in l2c_enable()
[all …]
|
| /kernel/linux/linux-6.6/arch/arm/mm/ |
| D | cache-l2x0.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mm/cache-l2x0.c - L210/L220/L310 cache controller support
20 #include <asm/hardware/cache-l2x0.h>
21 #include <asm/hardware/cache-aurora-l2.h>
22 #include "cache-tauros3.h"
63 * override this if they are running non-secure.
77 * register be written due to a work-around, as platforms running
78 * in non-secure mode may not be able to access this register.
109 * Enable the L2 cache controller. This function must only be
119 l2x0_data->configure(base); in l2c_enable()
[all …]
|
| /kernel/linux/linux-6.6/arch/arm/boot/dts/arm/ |
| D | arm-realview-pbx-a9.dts | 23 /dts-v1/;
24 #include "arm-realview-pbx.dtsi"
28 * This is the RealView Platform Baseboard Explore for Cortex-A9
31 model = "ARM RealView Platform Baseboard Explore for Cortex-A9";
35 #address-cells = <1>;
36 #size-cells = <0>;
37 enable-method = "arm,realview-smp";
39 cpu-map {
51 compatible = "arm,cortex-a9";
53 next-level-cache = <&L2>;
[all …]
|
| D | vexpress-v2p-ca9.dts | 1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A9 MPCore (V2P-CA9)
8 * HBI-0191B
11 /dts-v1/;
12 #include "vexpress-v2m.dtsi"
15 model = "V2P-CA9";
18 compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <1>;
21 #size-cells = <1>;
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/amdzen2/ |
| D | cache.json | 5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/amdzen2/ |
| D | cache.json | 5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
|
| /kernel/linux/linux-6.6/arch/arm/boot/dts/synaptics/ |
| D | berlin2q.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
6 #include <dt-bindings/clock/berlin2q.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 model = "Marvell Armada 1500 pro (BG2-Q) SoC";
12 #address-cells = <1>;
13 #size-cells = <1>;
21 #address-cells = <1>;
22 #size-cells = <0>;
23 enable-method = "marvell,berlin-smp";
[all …]
|