Searched +full:latch +full:- +full:ck (Results 1 – 11 of 11) sorted by relevance
10 - compatible: value should be either of the following.11 "mediatek,mt8135-mmc": for mmc host ip compatible with mt813512 "mediatek,mt8173-mmc": for mmc host ip compatible with mt817313 "mediatek,mt8183-mmc": for mmc host ip compatible with mt818314 "mediatek,mt8516-mmc": for mmc host ip compatible with mt851615 "mediatek,mt6779-mmc": for mmc host ip compatible with mt677916 "mediatek,mt2701-mmc": for mmc host ip compatible with mt270117 "mediatek,mt2712-mmc": for mmc host ip compatible with mt271218 "mediatek,mt7622-mmc": for MT7622 SoC19 "mediatek,mt7623-mmc", "mediatek,mt2701-mmc": for MT7623 SoC[all …]
1 # SPDX-License-Identifier: GPL-2.03 ---4 $id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Chaotian Jing <chaotian.jing@mediatek.com>11 - Wenbin Mei <wenbin.mei@mediatek.com>16 - enum:17 - mediatek,mt2701-mmc18 - mediatek,mt2712-mmc19 - mediatek,mt6779-mmc[all …]
1 /* SPDX-License-Identifier: GPL-2.0-only */6 * Tero Kristo (t-kristo@ti.com)16 s8 latch; member32 s8 latch; member87 #define CLK(dev, con, ck) \ argument93 .clk = ck, \142 * struct ti_dt_clk - OMAP DT clock alias declarations
5 * Tero Kristo (t-kristo@ti.com)24 s8 latch; member40 s8 latch; member95 #define CLK(dev, con, ck) \ argument101 .clk = ck, \150 * struct ti_dt_clk - OMAP DT clock alias declarations
1 // SPDX-License-Identifier: GPL-2.0-only7 /dts-v1/;8 #include <dt-bindings/gpio/gpio.h>14 compatible = "sony,xperia-m5", "mediatek,mt6795";15 chassis-type = "handset";30 reserved_memory: reserved-memory {31 #address-cells = <2>;32 #size-cells = <2>;38 no-map;42 preloader-region@44800000 {[all …]
1 // SPDX-License-Identifier: GPL-2.0-only3 * Copyright (c) 2014-2015 MediaTek Inc.10 #include <linux/dma-mapping.h>34 #include <linux/mmc/slot-gpio.h>40 /*--------------------------------------------------------------------------*/42 /*--------------------------------------------------------------------------*/49 /*--------------------------------------------------------------------------*/51 /*--------------------------------------------------------------------------*/85 /*--------------------------------------------------------------------------*/87 /*--------------------------------------------------------------------------*/[all …]
1 // SPDX-License-Identifier: GPL-2.0-only3 * Copyright (c) 2014-2015, 2022 MediaTek Inc.11 #include <linux/dma-mapping.h>34 #include <linux/mmc/slot-gpio.h>41 /*--------------------------------------------------------------------------*/43 /*--------------------------------------------------------------------------*/50 /*--------------------------------------------------------------------------*/52 /*--------------------------------------------------------------------------*/89 /*--------------------------------------------------------------------------*/91 /*--------------------------------------------------------------------------*/[all …]
3 * Copyright (c) 2007-2013 Broadcom Corporation13 * R - Read only14 * RC - Clear on read15 * RW - Read/Write16 * ST - Statistics register (clear on read)17 * W - Write only18 * WB - Wide bus register - the size is over 32 bits and it should be20 * WR - Write Clear (write 1 to clear the bit)32 /* [RW 1] Initiate the ATC array - reset all the valid bits */56 * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning -[all …]
1 // SPDX-License-Identifier: GPL-2.02 /* Copyright(c) 1999 - 2018 Intel Corporation. */34 static int debug = -1;108 * __ew32_prepare - prepare to write to MAC CSR register on certain parts123 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i) in __ew32_prepare()129 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) in __ew32()132 writel(val, hw->hw_addr + reg); in __ew32()136 * e1000_regdump - register printout routine146 switch (reginfo->ofs) { in e1000_regdump()160 pr_info("%-15s %08x\n", in e1000_regdump()[all …]
1 // SPDX-License-Identifier: GPL-2.02 /* Copyright(c) 1999 - 2018 Intel Corporation. */36 static int debug = -1;112 * __ew32_prepare - prepare to write to MAC CSR register on certain parts127 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i) in __ew32_prepare()133 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) in __ew32()136 writel(val, hw->hw_addr + reg); in __ew32()140 * e1000_regdump - register printout routine150 switch (reginfo->ofs) { in e1000_regdump()164 pr_info("%-15s %08x\n", in e1000_regdump()[all …]