| /kernel/linux/linux-6.6/Documentation/driver-api/surface_aggregator/clients/ |
| D | dtx.rst | 39 * **Latch:**
55 Latch States
58 The latch mechanism has two major states: *open* and *closed*. In the
62 The latch can additionally be locked and, correspondingly, unlocked, which
66 documentation for the detachment procedure below. By default, the latch is
82 instructions/commands. In case the latch is unlocked, the led will flash
83 green. If the latch has been locked, the led will be solid red
93 - If the latch is unlocked, the EC will open the latch and the clipboard
98 - If the latch is locked, the EC will *not* open the latch, meaning the
111 latch, after which the user can separate clipboard and base.
[all …]
|
| /kernel/linux/linux-6.6/include/linux/mfd/abx500/ |
| D | ab8500.h | 74 /* ab8500_irq_regoffset[0] -> IT[Source|Latch|Mask]1 */
83 /* ab8500_irq_regoffset[1] -> IT[Source|Latch|Mask]2 */
89 /* ab8500_irq_regoffset[2] -> IT[Source|Latch|Mask]3 */
98 /* ab8500_irq_regoffset[3] -> IT[Source|Latch|Mask]4 */
107 /* ab8500_irq_regoffset[4] -> IT[Source|Latch|Mask]5 */
116 /* ab8500_irq_regoffset[5] -> IT[Source|Latch|Mask]7 */
125 /* ab8500_irq_regoffset[6] -> IT[Source|Latch|Mask]8 */
134 /* ab8500_irq_regoffset[7] -> IT[Source|Latch|Mask]9 */
143 /* ab8500_irq_regoffset[8] -> IT[Source|Latch|Mask]10 */
152 /* ab8500_irq_regoffset[9] -> IT[Source|Latch|Mask]12 */
[all …]
|
| /kernel/linux/linux-5.10/include/linux/mfd/abx500/ |
| D | ab8500.h | 74 /* ab8500_irq_regoffset[0] -> IT[Source|Latch|Mask]1 */
83 /* ab8500_irq_regoffset[1] -> IT[Source|Latch|Mask]2 */
89 /* ab8500_irq_regoffset[2] -> IT[Source|Latch|Mask]3 */
98 /* ab8500_irq_regoffset[3] -> IT[Source|Latch|Mask]4 */
107 /* ab8500_irq_regoffset[4] -> IT[Source|Latch|Mask]5 */
116 /* ab8500_irq_regoffset[5] -> IT[Source|Latch|Mask]7 */
125 /* ab8500_irq_regoffset[6] -> IT[Source|Latch|Mask]8 */
134 /* ab8500_irq_regoffset[7] -> IT[Source|Latch|Mask]9 */
143 /* ab8500_irq_regoffset[8] -> IT[Source|Latch|Mask]10 */
152 /* ab8500_irq_regoffset[9] -> IT[Source|Latch|Mask]12 */
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/gpio/ |
| D | gpio-latch.yaml | 4 $id: http://devicetree.org/schemas/gpio/gpio-latch.yaml#
7 title: GPIO latch controller
43 of number of latches and the number of inputs per latch is derived from
48 const: gpio-latch
53 description: Array of GPIOs to be used to clock a latch
56 description: Array of GPIOs to be used as inputs per latch
59 description: Delay in nanoseconds to wait after the latch inputs have been
80 gpio-latch {
84 compatible = "gpio-latch";
|
| D | sprd,gpio-eic.yaml | 19 controller contains 4 sub-modules, i.e. EIC-debounce, EIC-latch, EIC-async and
32 The EIC-latch sub-module is used to latch some special power down signals
33 and generate interrupts, since the EIC-latch does not depend on the APB
48 - sprd,sc9860-eic-latch
58 - sprd,ums512-eic-latch
59 - const: sprd,sc9860-eic-latch
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/powerpc/power10/ |
| D | pmc.json | 55 "BriefDescription": "Cycles when the run latch is set and the core is in ST mode."
70 "BriefDescription": "Cycles when at least one thread has the run latch set."
80 "BriefDescription": "Cycles when the run latch is set for all threads."
90 "BriefDescription": "Cycles when this thread's run latch is set and the core is in SMT4 mode."
105 "BriefDescription": "Processor cycles gated by the run latch."
130 "BriefDescription": "Cycles when this thread's run latch is set and the core is in SMT2 mode."
200 "BriefDescription": "PowerPC instruction completed while the run latch is set."
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/gpio/ |
| D | gpio-eic-sprd.txt | 6 controller contains 4 sub-modules: EIC-debounce, EIC-latch, EIC-async and
19 The EIC-latch sub-module is used to latch some special power down signals
20 and generate interrupts, since the EIC-latch does not depend on the APB
33 "sprd,sc9860-eic-latch",
59 compatible = "sprd,sc9860-eic-latch";
|
| /kernel/linux/linux-6.6/drivers/clk/ti/ |
| D | mux.c | 81 ti_clk_latch(&mux->reg, mux->latch); in ti_clk_mux_set_parent()
125 s8 latch, u8 clk_mux_flags, u32 *table) in _register_mux() argument
146 mux->latch = latch; in _register_mux()
175 s32 latch = -EINVAL; in of_mux_clk_setup() local
194 of_property_read_u32(node, "ti,latch-bit", &latch); in of_mux_clk_setup()
211 flags, ®, shift, mask, latch, clk_mux_flags, in of_mux_clk_setup()
235 mux->latch = -EINVAL; in ti_clk_build_component_mux()
|
| /kernel/linux/linux-5.10/drivers/clk/ti/ |
| D | mux.c | 89 ti_clk_latch(&mux->reg, mux->latch); in ti_clk_mux_set_parent()
133 s8 latch, u8 clk_mux_flags, u32 *table) in _register_mux() argument
154 mux->latch = latch; in _register_mux()
183 s32 latch = -EINVAL; in of_mux_clk_setup() local
202 of_property_read_u32(node, "ti,latch-bit", &latch); in of_mux_clk_setup()
219 flags, ®, shift, mask, latch, clk_mux_flags, in of_mux_clk_setup()
243 mux->latch = -EINVAL; in ti_clk_build_component_mux()
|
| /kernel/linux/linux-5.10/arch/arm/mach-pxa/ |
| D | pcm990_baseboard.h | 46 #define PCM990_CTRL_LCDON 0x0002 /* RW LCD Latch on */
118 #define PCM990_IDE_IDEOE 0x0001 /* RW Latch on Databus */
119 #define PCM990_IDE_IDEON 0x0002 /* RW Latch on Control Address */
120 #define PCM990_IDE_IDEIN 0x0004 /* RW Latch on Interrupt usw. */
160 #define PCM990_CF_REG3_CFOE 0x0001 /* RW Latch on Databus */
161 #define PCM990_CF_REG3_CFON 0x0002 /* RW Latch on Control Address */
162 #define PCM990_CF_REG3_CFIN 0x0004 /* RW Latch on Interrupt usw. */
163 #define PCM990_CF_REG3_CFCD 0x0008 /* RW Latch on CD1/2 VS1/2 usw */
|
| /kernel/linux/linux-6.6/drivers/gpio/ |
| D | gpio-latch.c | 3 * GPIO latch driver
37 * the number of inputs per latch is derived from the number of GPIOs given
78 int latch = offset / priv->n_latched_gpios; in gpio_latch_set_unlocked() local
85 test_bit(latch * priv->n_latched_gpios + i, priv->shadow)); in gpio_latch_set_unlocked()
88 set(priv->clk_gpios->desc[latch], 1); in gpio_latch_set_unlocked()
90 set(priv->clk_gpios->desc[latch], 0); in gpio_latch_set_unlocked()
202 .compatible = "gpio-latch",
210 .name = "gpio-latch",
219 MODULE_DESCRIPTION("GPIO latch driver");
|
| /kernel/linux/linux-5.10/arch/arm/mach-pxa/include/mach/ |
| D | regs-uart.h | 22 #define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
23 #define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
38 #define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
39 #define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
54 #define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
55 #define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
73 #define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
74 #define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
102 #define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */
|
| /kernel/linux/linux-5.10/arch/sh/include/mach-common/mach/ |
| D | urquell.h | 60 #define LATCHCR_OFS 0x3000 /* Latch control register */
61 #define LATCUAR_OFS 0x3010 /* Latch upper address register */
62 #define LATCLAR_OFS 0x3012 /* Latch lower address register */
63 #define LATCLUDR_OFS 0x3024 /* Latch D31-16 register */
64 #define LATCLLDR_OFS 0x3026 /* Latch D15-0 register */
|
| /kernel/linux/linux-6.6/arch/sh/include/mach-common/mach/ |
| D | urquell.h | 60 #define LATCHCR_OFS 0x3000 /* Latch control register */
61 #define LATCUAR_OFS 0x3010 /* Latch upper address register */
62 #define LATCLAR_OFS 0x3012 /* Latch lower address register */
63 #define LATCLUDR_OFS 0x3024 /* Latch D31-16 register */
64 #define LATCLLDR_OFS 0x3026 /* Latch D15-0 register */
|
| /kernel/linux/linux-6.6/drivers/tty/serial/8250/ |
| D | 8250_uniphier.c | 21 * - Divisor latch at 9, no divisor latch access bit
30 /* Divisor Latch Register */
110 /* Divisor latch access bit does not exist. */ in uniphier_serial_out()
144 * This hardware does not have the divisor latch access bit.
145 * The divisor latch register exists at different address.
|
| /kernel/linux/linux-5.10/drivers/tty/serial/8250/ |
| D | 8250_uniphier.c | 21 * - Divisor latch at 9, no divisor latch access bit
30 /* Divisor Latch Register */
110 /* Divisor latch access bit does not exist. */ in uniphier_serial_out()
144 * This hardware does not have the divisor latch access bit.
145 * The divisor latch register exists at different address.
|
| /kernel/linux/linux-6.6/include/linux/ |
| D | seqlock.h | 638 * Latch sequence counters (seqcount_latch_t)
666 * raw_read_seqcount_latch() - pick even/odd latch data copy
686 * read_seqcount_latch() - pick even/odd latch data copy
731 * raw_write_seqcount_latch() - redirect latch readers to even/odd copy
742 * write_seqcount_latch_begin() - redirect latch readers to odd copy
745 * The latch technique is a multiversion concurrency control method that allows
752 * latch allows the same for non-atomic updates. The trade-off is doubling the
769 * void latch_modify(struct latch_struct *latch, ...)
771 * write_seqcount_latch_begin(&latch->seq);
772 * modify(latch->data[0], ...);
[all …]
|
| /kernel/linux/linux-6.6/kernel/time/ |
| D | clockevents.c | 32 static u64 cev_delta2ns(unsigned long latch, struct clock_event_device *evt, in cev_delta2ns() argument
35 u64 clc = (u64) latch << evt->shift; in cev_delta2ns()
44 * not equal latch, we know that the above shift overflowed. in cev_delta2ns()
46 if ((clc >> evt->shift) != (u64)latch) in cev_delta2ns()
59 * than latch by up to (mult - 1) >> shift. For the min_delta in cev_delta2ns()
62 * we would end up with a latch value larger than the upper in cev_delta2ns()
79 * clockevent_delta2ns - Convert a latch value (device ticks) to nanoseconds
80 * @latch: value to convert
83 * Math helper, returns latch value converted to nanoseconds (bound checked)
85 u64 clockevent_delta2ns(unsigned long latch, struct clock_event_device *evt) in clockevent_delta2ns() argument
[all …]
|
| /kernel/linux/linux-5.10/kernel/time/ |
| D | clockevents.c | 32 static u64 cev_delta2ns(unsigned long latch, struct clock_event_device *evt, in cev_delta2ns() argument
35 u64 clc = (u64) latch << evt->shift; in cev_delta2ns()
44 * not equal latch, we know that the above shift overflowed. in cev_delta2ns()
46 if ((clc >> evt->shift) != (u64)latch) in cev_delta2ns()
59 * than latch by up to (mult - 1) >> shift. For the min_delta in cev_delta2ns()
62 * we would end up with a latch value larger than the upper in cev_delta2ns()
79 * clockevents_delta2ns - Convert a latch value (device ticks) to nanoseconds
80 * @latch: value to convert
83 * Math helper, returns latch value converted to nanoseconds (bound checked)
85 u64 clockevent_delta2ns(unsigned long latch, struct clock_event_device *evt) in clockevent_delta2ns() argument
[all …]
|
| /kernel/linux/linux-6.6/arch/sh/include/asm/ |
| D | smc37c93x.h | 67 #define UART_DLL 0x0 /* Divisor Latch (LS) */
68 #define UART_DLM 0x2 /* Divisor Latch (MS) */
88 /* Alias for Divisor Latch Register */
127 #define LCR_DLAB 0x8000 /* Divisor Latch Access Bit */
|
| /kernel/linux/linux-5.10/arch/sh/include/asm/ |
| D | smc37c93x.h | 67 #define UART_DLL 0x0 /* Divisor Latch (LS) */
68 #define UART_DLM 0x2 /* Divisor Latch (MS) */
88 /* Alias for Divisor Latch Register */
127 #define LCR_DLAB 0x8000 /* Divisor Latch Access Bit */
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | armada3700-xtal-clock.txt | 4 reading the gpio latch register.
7 of the GPIO block where the gpio latch is located.
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | armada3700-xtal-clock.txt | 4 reading the gpio latch register.
7 of the GPIO block where the gpio latch is located.
|
| /kernel/linux/linux-5.10/arch/powerpc/platforms/powermac/ |
| D | time.c | 53 #define T1CL (4*RS) /* Timer 1 ctr/latch (low 8 bits) */
55 #define T1LL (6*RS) /* Timer 1 latch (low 8 bits) */
56 #define T1LH (7*RS) /* Timer 1 latch (high 8 bits) */
195 /* set the latch to `count' */ in via_calibrate_decr()
|
| /kernel/linux/linux-6.6/arch/powerpc/platforms/powermac/ |
| D | time.c | 53 #define T1CL (4*RS) /* Timer 1 ctr/latch (low 8 bits) */
55 #define T1LL (6*RS) /* Timer 1 latch (low 8 bits) */
56 #define T1LH (7*RS) /* Timer 1 latch (high 8 bits) */
195 /* set the latch to `count' */ in via_calibrate_decr()
|