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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/
Dxylon,logicvc-display.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Paul Kocialkowski <paul.kocialkowski@bootlin.com>
16 with Xilinx Zynq-7000 SoCs and Xilinx FPGAs.
20 synthesis time. As a result, many of the device-tree bindings are meant to
24 Layers are declared in the "layers" sub-node and have dedicated configuration.
25 In version 3 of the controller, each layer has fixed memory offset and address
32 - xylon,logicvc-3.02.a-display
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/inc/hw/
Dmpc.h1 /* Copyright 2012-15 Advanced Micro Devices, Inc.
26 * DOC: mpc-overview
29 * that performs blending of multiple planes, using global and per-pixel alpha.
30 * It also performs post-blending color correction operations according to the
62 * enum mpcc_alpha_blend_mode - define the alpha blend mode regarding pixel
63 * alpha and plane alpha values
67 * @MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA: per pixel alpha using DPP
68 * alpha value
73 * pixel alpha using DPP alpha value multiplied by a global gain (plane
74 * alpha)
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/sun4i/
Dsun4i_backend.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
14 #include <linux/dma-mapping.h>
35 /* backend <-> TCON muxing selection done in backend */
38 /* alpha at the lowest z position is not always supported */
55 regmap_write(engine->regs, SUN4I_BACKEND_OCCTL_REG, in sun4i_backend_apply_color_correction()
59 regmap_write(engine->regs, SUN4I_BACKEND_OCRCOEF_REG(i), in sun4i_backend_apply_color_correction()
68 regmap_update_bits(engine->regs, SUN4I_BACKEND_OCCTL_REG, in sun4i_backend_disable_color_correction()
76 regmap_write(engine->regs, SUN4I_BACKEND_REGBUFFCTL_REG, in sun4i_backend_commit()
82 int layer, bool enable) in sun4i_backend_layer_enable() argument
[all …]
Dsun8i_vi_layer.c1 // SPDX-License-Identifier: GPL-2.0-or-later
38 regmap_update_bits(mixer->engine.regs, in sun8i_vi_layer_enable()
43 regmap_update_bits(mixer->engine.regs, in sun8i_vi_layer_enable()
48 regmap_update_bits(mixer->engine.regs, in sun8i_vi_layer_enable()
57 regmap_update_bits(mixer->engine.regs, in sun8i_vi_layer_enable()
63 regmap_update_bits(mixer->engine.regs, in sun8i_vi_layer_enable()
77 if (mixer->cfg->is_de3) { in sun8i_vi_layer_update_alpha()
81 (plane->state->alpha >> 8); in sun8i_vi_layer_update_alpha()
83 val |= (plane->state->alpha == DRM_BLEND_ALPHA_OPAQUE) ? in sun8i_vi_layer_update_alpha()
87 regmap_update_bits(mixer->engine.regs, in sun8i_vi_layer_update_alpha()
[all …]
Dsun8i_mixer.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/dma-mapping.h>
90 /* for DE2 VI layer which ignores alpha */
99 /* for DE2 VI layer which ignores alpha */
108 /* for DE2 VI layer which ignores alpha */
117 /* for DE2 VI layer which ignores alpha */
126 /* for DE2 VI layer which ignores alpha */
135 /* for DE2 VI layer which ignores alpha */
144 /* for DE2 VI layer which ignores alpha */
153 /* for DE2 VI layer which ignores alpha */
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/sun4i/
Dsun4i_backend.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
14 #include <linux/dma-mapping.h>
34 /* backend <-> TCON muxing selection done in backend */
37 /* alpha at the lowest z position is not always supported */
54 regmap_write(engine->regs, SUN4I_BACKEND_OCCTL_REG, in sun4i_backend_apply_color_correction()
58 regmap_write(engine->regs, SUN4I_BACKEND_OCRCOEF_REG(i), in sun4i_backend_apply_color_correction()
67 regmap_update_bits(engine->regs, SUN4I_BACKEND_OCCTL_REG, in sun4i_backend_disable_color_correction()
75 regmap_write(engine->regs, SUN4I_BACKEND_REGBUFFCTL_REG, in sun4i_backend_commit()
81 int layer, bool enable) in sun4i_backend_layer_enable() argument
[all …]
Dsun8i_vi_layer.c1 // SPDX-License-Identifier: GPL-2.0-or-later
37 regmap_update_bits(mixer->engine.regs, in sun8i_vi_layer_enable()
42 regmap_update_bits(mixer->engine.regs, in sun8i_vi_layer_enable()
47 regmap_update_bits(mixer->engine.regs, in sun8i_vi_layer_enable()
56 regmap_update_bits(mixer->engine.regs, in sun8i_vi_layer_enable()
62 regmap_update_bits(mixer->engine.regs, in sun8i_vi_layer_enable()
73 struct drm_plane_state *state = plane->state; in sun8i_vi_layer_update_coord()
74 const struct drm_format_info *format = state->fb->format; in sun8i_vi_layer_update_coord()
89 src_w = drm_rect_width(&state->src) >> 16; in sun8i_vi_layer_update_coord()
90 src_h = drm_rect_height(&state->src) >> 16; in sun8i_vi_layer_update_coord()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/logicvc/
Dlogicvc_layer.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-2022 Bootlin
41 * What we call depth in this driver only counts color components, not alpha.
64 .alpha = true,
86 struct drm_device *drm_dev = drm_plane->dev; in logicvc_plane_atomic_check()
87 struct logicvc_layer *layer = logicvc_layer(drm_plane); in logicvc_plane_atomic_check() local
96 if (!new_state->crtc) in logicvc_plane_atomic_check()
99 crtc_state = drm_atomic_get_existing_crtc_state(new_state->state, in logicvc_plane_atomic_check()
100 new_state->crtc); in logicvc_plane_atomic_check()
102 return -EINVAL; in logicvc_plane_atomic_check()
[all …]
Dlogicvc_of.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-2022 Bootlin
14 { "lvds-4bits", LOGICVC_DISPLAY_INTERFACE_LVDS_4BITS },
15 { "lvds-3bits", LOGICVC_DISPLAY_INTERFACE_LVDS_3BITS },
33 { "layer", LOGICVC_LAYER_ALPHA_LAYER },
40 .name = "xylon,display-interface",
48 .name = "xylon,display-colorspace",
56 .name = "xylon,display-depth",
60 .name = "xylon,row-stride",
67 .name = "xylon,background-layer",
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/kernel/linux/linux-6.6/drivers/gpu/drm/xlnx/
Dzynqmp_disp.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
36 * enum zynqmp_dpsub_layer_id - Layer identifier
37 * @ZYNQMP_DPSUB_LAYER_VID: Video layer
38 * @ZYNQMP_DPSUB_LAYER_GFX: Graphics layer
46 * enum zynqmp_dpsub_layer_mode - Layer mode
47 * @ZYNQMP_DPSUB_LAYER_NONLIVE: non-live (memory) mode
48 * @ZYNQMP_DPSUB_LAYER_LIVE: live (stream) mode
[all …]
Dzynqmp_disp.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
19 #include <linux/dma-mapping.h>
33 * --------
38 * +------------------------------------------------------------+
39 * +--------+ | +----------------+ +-----------+ |
40 * | DPDMA | --->| | --> | Video | Video +-------------+ |
41 * | 4x vid | | | | | Rendering | -+--> | | | +------+
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/stm/
Dltdc.c1 // SPDX-License-Identifier: GPL-2.0
41 #define CRTC_MASK GENMASK(NB_CRTC - 1, 0)
54 #define REG_OFS_4 4 /* Insertion of "Layer Conf. 2" reg */
55 #define REG_OFS (ldev->caps.reg_ofs)
60 #define LTDC_LCR 0x0004 /* Layer Count */
78 /* Layer register offsets */
79 #define LTDC_L1LC1R (0x80) /* L1 Layer Configuration 1 */
80 #define LTDC_L1LC2R (0x84) /* L1 Layer Configuration 2 */
86 #define LTDC_L1CACR (0x98 + REG_OFS)/* L1 Constant Alpha Config */
116 #define GCR_PCPOL BIT(28) /* Pixel Clock POLarity-Inverted */
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/arm/
Dmalidp_planes.c1 // SPDX-License-Identifier: GPL-2.0-only
25 /* Layer specific register offsets */
56 * This 4-entry look-up-table is used to determine the full 8-bit alpha value
57 * for formats with 1- or 2-bit alpha channels.
58 * We set it to give 100%/0% opacity for 1-bit formats and 100%/66%/33%/0%
59 * opacity for 2-bit formats.
67 /* readahead for partial-frame prefetch */
79 * Replicate what the default ->reset hook does: free the state pointer and
85 struct malidp_plane_state *state = to_malidp_plane_state(plane->state); in malidp_plane_reset()
88 __drm_atomic_helper_plane_destroy_state(&state->base); in malidp_plane_reset()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/arm/
Dmalidp_planes.c1 // SPDX-License-Identifier: GPL-2.0-only
26 /* Layer specific register offsets */
57 * This 4-entry look-up-table is used to determine the full 8-bit alpha value
58 * for formats with 1- or 2-bit alpha channels.
59 * We set it to give 100%/0% opacity for 1-bit formats and 100%/66%/33%/0%
60 * opacity for 2-bit formats.
68 /* readahead for partial-frame prefetch */
72 * Replicate what the default ->reset hook does: free the state pointer and
78 struct malidp_plane_state *state = to_malidp_plane_state(plane->state); in malidp_plane_reset()
81 __drm_atomic_helper_plane_destroy_state(&state->base); in malidp_plane_reset()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/stm/
Dltdc.c1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/media-bus-format.h>
46 #define CRTC_MASK GENMASK(NB_CRTC - 1, 0)
61 #define LAY_OFS (ldev->caps.layer_ofs)
65 #define LTDC_LCR 0x0004 /* Layer Count */
86 /* Layer register offsets */
87 #define LTDC_L1C0R (ldev->caps.layer_regs[0]) /* L1 configuration 0 */
88 #define LTDC_L1C1R (ldev->caps.layer_regs[1]) /* L1 configuration 1 */
89 #define LTDC_L1RCR (ldev->caps.layer_regs[2]) /* L1 reload control */
90 #define LTDC_L1CR (ldev->caps.layer_regs[3]) /* L1 control register */
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/xlnx/
Dzynqmp_disp.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
27 #include <linux/dma-mapping.h>
43 * --------
48 * +------------------------------------------------------------+
49 * +--------+ | +----------------+ +-----------+ |
50 * | DPDMA | --->| | --> | Video | Video +-------------+ |
51 * | 4x vid | | | | | Rendering | -+--> | | | +------+
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/rockchip/
Drockchip_drm_vop2.c1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Author: Andy Yan <andy.yan@rock-chips.com>
12 #include <linux/media-bus-format.h>
34 #include <dt-bindings/soc/rockchip,vop2.h>
44 +----------+ +-------------+ +-----------+
47 +----------+ +-------------+ +---------------+ +-------------+ +-----------+
48 +----------+ +-------------+ |N from 6 layers| | |
49 | Cluster | | Sel 1 from 6| | Overlay0 +--->| Video Port0 | +-----------+
51 +----------+ +-------------+ +---------------+ +-------------+ | LVDS |
52 +----------+ +-------------+ +-----------+
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/inc/hw/
Dmpc.h1 /* Copyright 2012-15 Advanced Micro Devices, Inc.
66 enum mpcc_alpha_blend_mode alpha_mode; /* alpha blend mode */
67 bool pre_multiplied_alpha; /* alpha pre-multiplied mode flag */
88 /* 0-single plane,2-row subsampling,4-column subsampling,6-checkboard subsampling */
90 /* 0- disable frame alternate, 1- enable frame alternate */
92 /* 0- disable field alternate, 1- enable field alternate */
94 /* 0-no force,2-force frame polarity from top,3-force frame polarity from bottom */
96 /* 0-no force,2-force field polarity from top,3-force field polarity from bottom */
123 struct mpcc *mpcc_bot; /* pointer to bottom layer MPCC. NULL when not connected */
136 struct mpcc *opp_list; /* The top MPCC layer of the MPC tree that outputs to OPP endpoint */
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/atmel-hlcdc/
Datmel_hlcdc_plane.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
10 #include <linux/mfd/atmel-hlcdc.h>
126 static int atmel_hlcdc_format_to_plane_mode(u32 format, u32 *mode) in atmel_hlcdc_format_to_plane_mode() argument
130 *mode = ATMEL_HLCDC_C8_MODE; in atmel_hlcdc_format_to_plane_mode()
133 *mode = ATMEL_HLCDC_XRGB4444_MODE; in atmel_hlcdc_format_to_plane_mode()
136 *mode = ATMEL_HLCDC_ARGB4444_MODE; in atmel_hlcdc_format_to_plane_mode()
139 *mode = ATMEL_HLCDC_RGBA4444_MODE; in atmel_hlcdc_format_to_plane_mode()
142 *mode = ATMEL_HLCDC_RGB565_MODE; in atmel_hlcdc_format_to_plane_mode()
145 *mode = ATMEL_HLCDC_RGB888_MODE; in atmel_hlcdc_format_to_plane_mode()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/atmel-hlcdc/
Datmel_hlcdc_plane.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
10 #include <linux/mfd/atmel-hlcdc.h>
23 * struct atmel_hlcdc_plane_state - Atmel HLCDC Plane state structure.
128 static int atmel_hlcdc_format_to_plane_mode(u32 format, u32 *mode) in atmel_hlcdc_format_to_plane_mode() argument
132 *mode = ATMEL_HLCDC_C8_MODE; in atmel_hlcdc_format_to_plane_mode()
135 *mode = ATMEL_HLCDC_XRGB4444_MODE; in atmel_hlcdc_format_to_plane_mode()
138 *mode = ATMEL_HLCDC_ARGB4444_MODE; in atmel_hlcdc_format_to_plane_mode()
141 *mode = ATMEL_HLCDC_RGBA4444_MODE; in atmel_hlcdc_format_to_plane_mode()
144 *mode = ATMEL_HLCDC_RGB565_MODE; in atmel_hlcdc_format_to_plane_mode()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/sprd/
Dsprd_dpu.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/dma-buf.h>
70 /* Layer control bits */
130 struct dpu_context *ctx = &dpu->ctx; in dpu_wait_stop_done()
133 if (ctx->stopped) in dpu_wait_stop_done()
136 rc = wait_event_interruptible_timeout(ctx->wait_queue, ctx->evt_stop, in dpu_wait_stop_done()
138 ctx->evt_stop = false; in dpu_wait_stop_done()
140 ctx->stopped = true; in dpu_wait_stop_done()
143 drm_err(dpu->drm, "dpu wait for stop done time out!\n"); in dpu_wait_stop_done()
144 return -ETIMEDOUT; in dpu_wait_stop_done()
[all …]
/kernel/linux/linux-5.10/drivers/video/fbdev/
Ds3c-fb.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* linux/drivers/video/s3c-fb.c
5 * Copyright 2008-2010 Simtec Electronics
15 #include <linux/dma-mapping.h>
31 * setting of the alpha-blending functions that each window has, so only
35 * output timings and as the control for the output power-down state.
38 /* note, the previous use of <mach/regs-fb.h> to get platform specific data
58 #define VALID_BPP(x) (1 << ((x) - 1))
67 * struct s3c_fb_variant - fb variant information
110 * @has_osd_alpha: Set if can change alpha transparency for a window.
[all …]
/kernel/linux/linux-6.6/drivers/video/fbdev/
Ds3c-fb.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* linux/drivers/video/s3c-fb.c
5 * Copyright 2008-2010 Simtec Electronics
15 #include <linux/dma-mapping.h>
31 * setting of the alpha-blending functions that each window has, so only
35 * output timings and as the control for the output power-down state.
38 /* note, the previous use of <mach/regs-fb.h> to get platform specific data
58 #define VALID_BPP(x) (1 << ((x) - 1))
67 * struct s3c_fb_variant - fb variant information
111 * @has_osd_alpha: Set if can change alpha transparency for a window.
[all …]
/kernel/linux/linux-5.10/Documentation/driver-api/media/drivers/
Dcx2341x-devel.rst1 .. SPDX-License-Identifier: GPL-2.0
7 -----------------------
12 .. note:: the memory long words are little-endian ('intel format').
21 .. code-block:: none
23 ivtvctl -O min=0x02000000,max=0x020000ff
26 register space :-).
35 .. code-block:: none
37 0x00000000-0x00ffffff Encoder memory space
38 0x00000000-0x0003ffff Encode.rom
39 ???-??? MPEG buffer(s)
[all …]
/kernel/linux/linux-6.6/Documentation/driver-api/media/drivers/
Dcx2341x-devel.rst1 .. SPDX-License-Identifier: GPL-2.0
7 -----------------------
12 .. note:: the memory long words are little-endian ('intel format').
21 .. code-block:: none
23 ivtvctl -O min=0x02000000,max=0x020000ff
26 register space :-).
35 .. code-block:: none
37 0x00000000-0x00ffffff Encoder memory space
38 0x00000000-0x0003ffff Encode.rom
39 ???-??? MPEG buffer(s)
[all …]

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