Searched +full:legacy +full:- +full:interrupt +full:- +full:controller (Results 1 – 25 of 804) sorted by relevance
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | uniphier-pcie.txt | 1 Socionext UniPhier PCIe host controller bindings
3 This describes the devicetree bindings for PCIe host controller implemented
6 UniPhier PCIe host controller is based on the Synopsys DesignWare PCI core.
9 Documentation/devicetree/bindings/pci/designware-pcie.txt.
12 - compatible: Should be "socionext,uniphier-pcie".
13 - reg: Specifies offset and length of the register set for the device.
14 According to the reg-names, appropriate register sets are required.
15 - reg-names: Must include the following entries:
16 "dbi" - controller configuration registers
17 "link" - SoC-specific glue layer registers
[all …]
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| D | xilinx-nwl-pcie.txt | 4 - compatible: Should contain "xlnx,nwl-pcie-2.11"
5 - #address-cells: Address representation for root ports, set to <3>
6 - #size-cells: Size representation for root ports, set to <2>
7 - #interrupt-cells: specifies the number of cells needed to encode an
8 interrupt source. The value must be 1.
9 - reg: Should contain Bridge, PCIe Controller registers location,
11 - reg-names: Must include the following entries:
13 "pcireg": PCIe controller registers
15 - device_type: must be "pci"
16 - interrupts: Should contain NWL PCIe interrupt
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| D | rockchip-pcie-host.txt | 4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
7 interrupt source. The value must be 1.
8 - compatible: Should contain "rockchip,rk3399-pcie"
9 - reg: Two register ranges as listed in the reg-names property
10 - reg-names: Must include the following names
11 - "axi-base"
12 - "apb-base"
13 - clocks: Must contain an entry for each entry in clock-names.
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| D | pci-keystone.txt | 3 Keystone PCI host Controller is based on the Synopsys DesignWare PCI
6 Documentation/devicetree/bindings/pci/designware-pcie.txt
8 Please refer to Documentation/devicetree/bindings/pci/designware-pcie.txt
12 Required Properties:-
14 compatibility: Should be "ti,keystone-pcie" for RC on Keystone2 SoC
15 Should be "ti,am654-pcie-rc" for RC on AM654x SoC
16 reg: Three register ranges as listed in the reg-names property
17 reg-names: "dbics" for the DesignWare PCIe registers, "app" for the
21 pcie_msi_intc : Interrupt controller device node for MSI IRQ chip
22 interrupt-cells: should be set to 1
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/ |
| D | rockchip-dw-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DesignWare based PCIe controller on Rockchip SoCs
10 - Shawn Lin <shawn.lin@rock-chips.com>
11 - Simon Xue <xxm@rock-chips.com>
12 - Heiko Stuebner <heiko@sntech.de>
15 RK3568 SoC PCIe host controller is based on the Synopsys DesignWare
17 snps,dw-pcie.yaml.
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| D | xlnx,nwl-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/xlnx,nwl-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thippeswamy Havalige <thippeswamy.havalige@amd.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
14 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
18 const: xlnx,nwl-pcie-2.11
22 - description: PCIe bridge registers location.
23 - description: PCIe Controller registers location.
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| D | rockchip,rk3399-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Lin <shawn.lin@rock-chips.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
14 - $ref: rockchip,rk3399-pcie-common.yaml#
18 const: rockchip,rk3399-pcie
22 reg-names:
24 - const: axi-base
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| /kernel/linux/linux-5.10/Documentation/core-api/irq/ |
| D | irq-domain.rst | 2 The irq_domain interrupt number mapping library
7 This is simple when there is only one interrupt controller, but in
8 systems with multiple interrupt controllers the kernel must ensure
9 that each one gets assigned non-overlapping allocations of Linux
12 The number of interrupt controllers registered as unique irqchips
15 mechanisms as the IRQ core system by modelling their interrupt
16 handlers as irqchips, i.e. in effect cascading interrupt controllers.
18 Here the interrupt number loose all kind of correspondence to
19 hardware interrupt numbers: whereas in the past, IRQ numbers could
21 interrupt controller (i.e. the component actually fireing the
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| /kernel/linux/linux-6.6/Documentation/core-api/irq/ |
| D | irq-domain.rst | 2 The irq_domain interrupt number mapping library
7 This is simple when there is only one interrupt controller, but in
8 systems with multiple interrupt controllers the kernel must ensure
9 that each one gets assigned non-overlapping allocations of Linux
12 The number of interrupt controllers registered as unique irqchips
15 mechanisms as the IRQ core system by modelling their interrupt
16 handlers as irqchips, i.e. in effect cascading interrupt controllers.
18 Here the interrupt number loose all kind of correspondence to
19 hardware interrupt numbers: whereas in the past, IRQ numbers could
21 interrupt controller (i.e. the component actually fireing the
[all …]
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| /kernel/linux/linux-6.6/Documentation/PCI/ |
| D | boot-interrupts.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 :Author: - Sean V Kelley <sean.v.kelley@linux.intel.com>
13 interrupt messages (Assert_INTx/Deassert_INTx). The integrated IO-APIC in a
14 given Core IO converts the legacy interrupt messages from PCI Express to
15 MSI interrupts. If the IO-APIC is disabled (via the mask bits in the
16 IO-APIC table entries), the messages are routed to the legacy PCH. This
17 in-band interrupt mechanism was traditionally necessary for systems that
18 did not support the IO-APIC and for boot. Intel in the past has used the
20 protocol describes this in-band legacy wire-interrupt INTx mechanism for
21 I/O devices to signal PCI-style level interrupts. The subsequent paragraphs
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| /kernel/linux/linux-5.10/Documentation/PCI/ |
| D | boot-interrupts.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 :Author: - Sean V Kelley <sean.v.kelley@linux.intel.com>
13 interrupt messages (Assert_INTx/Deassert_INTx). The integrated IO-APIC in a
14 given Core IO converts the legacy interrupt messages from PCI Express to
15 MSI interrupts. If the IO-APIC is disabled (via the mask bits in the
16 IO-APIC table entries), the messages are routed to the legacy PCH. This
17 in-band interrupt mechanism was traditionally necessary for systems that
18 did not support the IO-APIC and for boot. Intel in the past has used the
20 protocol describes this in-band legacy wire-interrupt INTx mechanism for
21 I/O devices to signal PCI-style level interrupts. The subsequent paragraphs
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | nvidia,tegra20-ictlr.txt | 1 NVIDIA Legacy Interrupt Controller
3 All Tegra SoCs contain a legacy interrupt controller that routes
7 The HW block exposes a number of interrupt controllers, each
12 - compatible : should be: "nvidia,tegra<chip>-ictlr". The LIC on
13 subsequent SoCs remained backwards-compatible with Tegra30, so on
15 include "nvidia,tegra30-ictlr".
16 - reg : Specifies base physical address and size of the registers.
17 Each controller must be described separately (Tegra20 has 4 of them,
19 - interrupt-controller : Identifies the node as an interrupt controller.
20 - #interrupt-cells : Specifies the number of cells needed to encode an
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/interrupt-controller/ |
| D | nvidia,tegra20-ictlr.txt | 1 NVIDIA Legacy Interrupt Controller
3 All Tegra SoCs contain a legacy interrupt controller that routes
7 The HW block exposes a number of interrupt controllers, each
12 - compatible : should be: "nvidia,tegra<chip>-ictlr". The LIC on
13 subsequent SoCs remained backwards-compatible with Tegra30, so on
15 include "nvidia,tegra30-ictlr".
16 - reg : Specifies base physical address and size of the registers.
17 Each controller must be described separately (Tegra20 has 4 of them,
19 - interrupt-controller : Identifies the node as an interrupt controller.
20 - #interrupt-cells : Specifies the number of cells needed to encode an
[all …]
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| /kernel/linux/linux-5.10/arch/x86/include/asm/ |
| D | x86_init.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
16 * struct x86_init_mpparse - platform specific mpparse ops
28 * struct x86_init_resources - platform specific resource related ops
42 * struct x86_init_irqs - platform specific interrupt setup
43 * @pre_vector_init: init code to run before interrupt vectors
45 * @intr_init: interrupt init code
46 * @intr_mode_select: interrupt delivery mode selection
47 * @intr_mode_init: interrupt delivery mode setup
48 * @create_pci_msi_domain: Create the PCI/MSI interrupt domain
59 * struct x86_init_oem - oem platform specific customizing functions
[all …]
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| /kernel/linux/linux-6.6/arch/x86/include/asm/ |
| D | x86_init.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
16 * struct x86_init_mpparse - platform specific mpparse ops
28 * struct x86_init_resources - platform specific resource related ops
43 * struct x86_init_irqs - platform specific interrupt setup
44 * @pre_vector_init: init code to run before interrupt vectors
46 * @intr_init: interrupt init code
47 * @intr_mode_select: interrupt delivery mode selection
48 * @intr_mode_init: interrupt delivery mode setup
49 * @create_pci_msi_domain: Create the PCI/MSI interrupt domain
60 * struct x86_init_oem - oem platform specific customizing functions
[all …]
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| /kernel/linux/linux-6.6/Documentation/arch/loongarch/ |
| D | irq-chip-model.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 Currently, LoongArch based processors (e.g. Loongson-3A5000) can only work together
9 Interrupt Controller), LIOINTC (Legacy I/O Interrupt Controller), EIOINTC (Extended
10 I/O Interrupt Controller), HTVECINTC (Hyper-Transport Vector Interrupt Controller),
11 PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
12 in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
14 CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package
15 controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e.,
17 and there are two models of hierarchy (legacy model and extended model).
19 Legacy IRQ model
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| /kernel/linux/linux-5.10/drivers/mtd/nand/raw/ |
| D | tmio_nand.c | 2 * Toshiba TMIO NAND flash controller driver
4 * Slightly murky pre-git history of the driver:
34 #include <linux/interrupt.h>
42 /*--------------------------------------------------------------------------*/
45 * NAND Flash Host Controller Configuration Register
49 #define CCR_INTP 0x3d /* b Interrupt Pin */
50 #define CCR_INTE 0x48 /* b Interrupt Enable */
65 #define FCR_ISR 0x06 /* b Interrupt Status Register */
66 #define FCR_IMR 0x07 /* b Interrupt Mask Register */
73 #define FCR_MODE_HWECC_CALC 0xB4 /* HW-ECC Data */
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/gpio/ |
| D | ti,omap-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/ti,omap-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: OMAP GPIO controller
10 - Grygorii Strashko <grygorii.strashko@ti.com>
13 The general-purpose interface combines general-purpose input/output (GPIO) banks.
14 Each GPIO banks provides up to 32 dedicated general-purpose pins with input
15 and output capabilities; interrupt generation in active mode and wake-up
21 - enum:
[all …]
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| /kernel/linux/linux-6.6/arch/powerpc/sysdev/ |
| D | i8259.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * i8259 interrupt controller driver.
8 #include <linux/interrupt.h>
26 * Acknowledge the IRQ using either the PCI host bridge's interrupt
29 * IBM and Motorola PReP boxes so we must use the int-ack feature on them.
36 /* Either int-ack or poll for the IRQ */ in i8259_irq()
43 /* Perform an interrupt acknowledge cycle on controller 1. */ in i8259_irq()
48 * Interrupt is cascaded so perform interrupt in i8259_irq()
49 * acknowledge on controller 2. in i8259_irq()
58 * This may be a spurious interrupt. in i8259_irq()
[all …]
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| /kernel/linux/linux-5.10/arch/powerpc/sysdev/ |
| D | i8259.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * i8259 interrupt controller driver.
8 #include <linux/interrupt.h>
26 * Acknowledge the IRQ using either the PCI host bridge's interrupt
29 * IBM and Motorola PReP boxes so we must use the int-ack feature on them.
36 /* Either int-ack or poll for the IRQ */ in i8259_irq()
43 /* Perform an interrupt acknowledge cycle on controller 1. */ in i8259_irq()
48 * Interrupt is cascaded so perform interrupt in i8259_irq()
49 * acknowledge on controller 2. in i8259_irq()
58 * This may be a spurious interrupt. in i8259_irq()
[all …]
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| /kernel/linux/linux-6.6/arch/parisc/include/asm/ |
| D | superio.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
11 #define SIO_FDCBAR 0x90 /* Floppy Disk Controller BAR */
19 /* Interrupt Routing Control registers */
30 #define CFG_IR_LOW CFG_IR_SER /* Lowest interrupt routing reg */
31 #define CFG_IR_HIGH CFG_IR_ACPI /* Highest interrupt routing reg */
34 #define OCW2_EOI 0x20 /* Non-specific EOI */
38 #define OCW3_POLL 0x0C /* Poll the PIC for an interrupt vector */
40 /* Interrupt lines. Only PIC1 is used */
45 #define FDC_IRQ 6 /* Floppy controller */
60 struct pci_dev *lio_pdev; /* pci device for legacy IO (fn 1) */
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| /kernel/linux/linux-5.10/arch/parisc/include/asm/ |
| D | superio.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
11 #define SIO_FDCBAR 0x90 /* Floppy Disk Controller BAR */
19 /* Interrupt Routing Control registers */
30 #define CFG_IR_LOW CFG_IR_SER /* Lowest interrupt routing reg */
31 #define CFG_IR_HIGH CFG_IR_ACPI /* Highest interrupt routing reg */
34 #define OCW2_EOI 0x20 /* Non-specific EOI */
38 #define OCW3_POLL 0x0C /* Poll the PIC for an interrupt vector */
40 /* Interrupt lines. Only PIC1 is used */
45 #define FDC_IRQ 6 /* Floppy controller */
60 struct pci_dev *lio_pdev; /* pci device for legacy IO (fn 1) */
[all …]
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| /kernel/linux/linux-6.6/arch/powerpc/boot/dts/ |
| D | currituck.dts | 11 /dts-v1/;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 dcr-parent = <&{/cpus/cpu@0}>;
27 #address-cells = <1>;
28 #size-cells = <0>;
34 clock-frequency = <1600000000>; // 1.6 GHz
35 timebase-frequency = <100000000>; // 100Mhz
36 i-cache-line-size = <32>;
37 d-cache-line-size = <32>;
[all …]
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| /kernel/linux/linux-5.10/arch/powerpc/boot/dts/ |
| D | currituck.dts | 11 /dts-v1/;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 dcr-parent = <&{/cpus/cpu@0}>;
27 #address-cells = <1>;
28 #size-cells = <0>;
34 clock-frequency = <1600000000>; // 1.6 GHz
35 timebase-frequency = <100000000>; // 100Mhz
36 i-cache-line-size = <32>;
37 d-cache-line-size = <32>;
[all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/rockchip/ |
| D | rk3588.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "rk3588-pinctrl.dtsi"
11 compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
16 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
21 compatible = "rockchip,rk3588-i2s-tdm";
25 clock-names = "mclk_tx", "mclk_rx", "hclk";
26 assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;
27 assigned-clock-parents = <&cru PLL_AUPLL>;
29 dma-names = "tx";
30 power-domains = <&power RK3588_PD_VO0>;
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