| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pinctrl/ |
| D | intel,lgm-io.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/intel,lgm-io.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rahul Tanwar <rahul.tanwar@linux.intel.com>
18 const: intel,lgm-io
25 '-pins$':
30 $ref: pinmux-node.yaml#
37 bias-pull-up: true
38 bias-pull-down: true
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/ |
| D | intel,lgm-io.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/intel,lgm-io.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rahul Tanwar <rahul.tanwar@linux.intel.com>
18 const: intel,lgm-io
25 '-pins$':
30 $ref: pinmux-node.yaml#
37 bias-pull-up: true
38 bias-pull-down: true
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/mfd/ |
| D | syscon.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 represent as any specific type of device. The typical use-case is
13 for some other node's driver, or platform-specific code, to acquire
20 - Lee Jones <lee@kernel.org>
27 - syscon
30 - compatible
35 - items:
36 - enum:
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| /kernel/linux/linux-5.10/drivers/pci/controller/dwc/ |
| D | pcie-intel-gw.c | 1 // SPDX-License-Identifier: GPL-2.0
18 #include "pcie-designware.h"
20 #define PORT_AFR_N_FTS_GEN12_DFT (SZ_128 - 1)
90 return readl(lpp->app_base + ofs); in pcie_app_rd()
95 writel(val, lpp->app_base + ofs); in pcie_app_wr()
101 pcie_update_bits(lpp->app_base, ofs, mask, val); in pcie_app_wr_mask()
106 return dw_pcie_readl_dbi(&lpp->pci, ofs); in pcie_rc_cfg_rd()
111 dw_pcie_writel_dbi(&lpp->pci, ofs, val); in pcie_rc_cfg_wr()
117 pcie_update_bits(lpp->pci.dbi_base, ofs, mask, val); in pcie_rc_cfg_wr_mask()
134 u8 offset = dw_pcie_find_capability(&lpp->pci, PCI_CAP_ID_EXP); in intel_pcie_link_setup()
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| /kernel/linux/linux-5.10/drivers/pinctrl/ |
| D | pinctrl-equilibrium.c | 1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/pinctrl/pinconf-generic.h>
18 #include "pinctrl-equilibrium.h"
20 #define PIN_NAME_FMT "io-%d"
31 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_gpio_disable_irq()
32 writel(BIT(offset), gctrl->membase + GPIO_IRNENCLR); in eqbr_gpio_disable_irq()
33 raw_spin_unlock_irqrestore(&gctrl->lock, flags); in eqbr_gpio_disable_irq()
43 gc->direction_input(gc, offset); in eqbr_gpio_enable_irq()
44 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_gpio_enable_irq()
45 writel(BIT(offset), gctrl->membase + GPIO_IRNRNSET); in eqbr_gpio_enable_irq()
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| /kernel/linux/linux-6.6/drivers/pinctrl/ |
| D | pinctrl-equilibrium.c | 1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/pinctrl/pinconf-generic.h>
19 #include "pinctrl-equilibrium.h"
21 #define PIN_NAME_FMT "io-%d"
32 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_gpio_disable_irq()
33 writel(BIT(offset), gctrl->membase + GPIO_IRNENCLR); in eqbr_gpio_disable_irq()
34 raw_spin_unlock_irqrestore(&gctrl->lock, flags); in eqbr_gpio_disable_irq()
45 gc->direction_input(gc, offset); in eqbr_gpio_enable_irq()
47 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_gpio_enable_irq()
48 writel(BIT(offset), gctrl->membase + GPIO_IRNRNSET); in eqbr_gpio_enable_irq()
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| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
66 will be called pinctrl-apple-gpio.
69 bool "Axis ARTPEC-6 pin controller driver"
74 This is the driver for the Axis ARTPEC-6 pin controller. This driver
77 found in Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
86 functionality. This driver supports the pinmux, push-pull and
117 tristate "X-Powers AXP209 PMIC pinctrl and GPIO Support"
150 called pinctrl-cy8c95x0.
153 tristate "TI DA850/OMAP-L138/AM18XX pull-up and pull-down groups"
158 Driver for TI DA850/OMAP-L138/AM18XX pinconf. Used to control
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| /kernel/linux/linux-6.6/drivers/tty/serial/ |
| D | lantiq.c | 1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/io.h>
144 u32 fstat = __raw_readl(port->membase + LTQ_ASC_FSTAT); in lqasc_tx_ready()
156 spin_lock_irqsave(<q_port->lock, flags); in lqasc_start_tx()
159 writeb(ch, port->membase + LTQ_ASC_TBUF)); in lqasc_start_tx()
160 spin_unlock_irqrestore(<q_port->lock, flags); in lqasc_start_tx()
167 __raw_writel(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE); in lqasc_stop_rx()
173 struct tty_port *tport = &port->state->port; in lqasc_rx_chars()
176 fifocnt = __raw_readl(port->membase + LTQ_ASC_FSTAT) & in lqasc_rx_chars()
178 while (fifocnt--) { in lqasc_rx_chars()
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| /kernel/linux/linux-5.10/drivers/tty/serial/ |
| D | lantiq.c | 1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/io.h>
150 spin_lock_irqsave(<q_port->lock, flags); in lqasc_start_tx()
152 spin_unlock_irqrestore(<q_port->lock, flags); in lqasc_start_tx()
159 __raw_writel(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE); in lqasc_stop_rx()
165 struct tty_port *tport = &port->state->port; in lqasc_rx_chars()
168 fifocnt = __raw_readl(port->membase + LTQ_ASC_FSTAT) & in lqasc_rx_chars()
170 while (fifocnt--) { in lqasc_rx_chars()
172 ch = readb(port->membase + LTQ_ASC_RBUF); in lqasc_rx_chars()
173 rsr = (__raw_readl(port->membase + LTQ_ASC_STATE) in lqasc_rx_chars()
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| /kernel/linux/linux-5.10/drivers/spi/ |
| D | spi-lantiq-ssc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011-2015 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
4 * Copyright (C) 2016 Hauke Mehrtens <hauke@hauke-m.de>
11 #include <linux/io.h>
141 #define LTQ_SPI_RXCNT_TODO_M 0xFFFF /* Recevie to-do value */
190 return __raw_readl(spi->regbase + reg); in lantiq_ssc_readl()
196 __raw_writel(val, spi->regbase + reg); in lantiq_ssc_writel()
202 u32 val = __raw_readl(spi->regbase + reg); in lantiq_ssc_maskl()
206 __raw_writel(val, spi->regbase + reg); in lantiq_ssc_maskl()
211 const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg; in tx_fifo_level()
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| /kernel/linux/linux-6.6/drivers/spi/ |
| D | spi-lantiq-ssc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011-2015 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
4 * Copyright (C) 2016 Hauke Mehrtens <hauke@hauke-m.de>
12 #include <linux/io.h>
142 #define LTQ_SPI_RXCNT_TODO_M 0xFFFF /* Recevie to-do value */
191 return __raw_readl(spi->regbase + reg); in lantiq_ssc_readl()
197 __raw_writel(val, spi->regbase + reg); in lantiq_ssc_writel()
203 u32 val = __raw_readl(spi->regbase + reg); in lantiq_ssc_maskl()
207 __raw_writel(val, spi->regbase + reg); in lantiq_ssc_maskl()
212 const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg; in tx_fifo_level()
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| D | spi-cadence-quadspi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 // Copyright Altera Corporation (C) 2012-2014. All rights reserved.
6 // Copyright Intel Corporation (C) 2019-2020. All rights reserved.
7 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
12 #include <linux/dma-mapping.h>
16 #include <linux/firmware/xlnx-zynqmp.h>
18 #include <linux/io.h>
30 #include <linux/spi/spi-mem.h>
33 #define CQSPI_NAME "cadence-qspi"
304 u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_is_idle()
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| /kernel/linux/patches/linux-5.10/imx8mm_patch/patches/drivers/ |
| D | 0030_linux_drivers_pci_misc_nvmem_of_mtd_mmc.patch | 7 Change-Id: Iec160bd007994d82f416debdccfbc0d9bdb40470
9 diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
11 --- a/drivers/misc/Kconfig
13 @@ -314,6 +314,26 @@ config ISL29020
40 diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
42 --- a/drivers/misc/Makefile
44 @@ -19,6 +19,8 @@ obj-$(CONFIG_TIFM_7XX1) += tifm_7xx1.o
45 obj-$(CONFIG_PHANTOM) += phantom.o
46 obj-$(CONFIG_QCOM_COINCELL) += qcom-coincell.o
47 obj-$(CONFIG_QCOM_FASTRPC) += fastrpc.o
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| /kernel/linux/linux-6.6/ |
| D | MAINTAINERS | 5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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| /kernel/linux/patches/linux-5.10/hispark_taurus_patch/ |
| D | hispark_taurus.patch | 1 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
3 --- a/arch/arm/Kconfig
5 @@ -322,7 +322,7 @@ config ARCH_MULTIPLATFORM
9 - select AUTO_ZRELADDR
14 @@ -650,6 +650,8 @@ source "arch/arm/mach-highbank/Kconfig"
16 source "arch/arm/mach-hisi/Kconfig"
18 +source "arch/arm/mach-hibvt/Kconfig"
20 source "arch/arm/mach-imx/Kconfig"
22 source "arch/arm/mach-integrator/Kconfig"
23 diff --git a/arch/arm/Makefile b/arch/arm/Makefile
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