| /kernel/linux/linux-5.10/drivers/clk/sprd/ |
| D | sc9860-clk.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/sprd,sc9860-clk.h>
25 static CLK_FIXED_FACTOR(fac_4m, "fac-4m", "ext-26m",
27 static CLK_FIXED_FACTOR(fac_2m, "fac-2m", "ext-26m",
29 static CLK_FIXED_FACTOR(fac_1m, "fac-1m", "ext-26m",
31 static CLK_FIXED_FACTOR(fac_250k, "fac-250k", "ext-26m",
33 static CLK_FIXED_FACTOR(fac_rpll0_26m, "rpll0-26m", "ext-26m",
35 static CLK_FIXED_FACTOR(fac_rpll1_26m, "rpll1-26m", "ext-26m",
37 static CLK_FIXED_FACTOR(fac_rco_25m, "rco-25m", "ext-rc0-100m",
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/sprd/ |
| D | sc9860-clk.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/sprd,sc9860-clk.h>
25 static CLK_FIXED_FACTOR(fac_4m, "fac-4m", "ext-26m",
27 static CLK_FIXED_FACTOR(fac_2m, "fac-2m", "ext-26m",
29 static CLK_FIXED_FACTOR(fac_1m, "fac-1m", "ext-26m",
31 static CLK_FIXED_FACTOR(fac_250k, "fac-250k", "ext-26m",
33 static CLK_FIXED_FACTOR(fac_rpll0_26m, "rpll0-26m", "ext-26m",
35 static CLK_FIXED_FACTOR(fac_rpll1_26m, "rpll1-26m", "ext-26m",
37 static CLK_FIXED_FACTOR(fac_rco_25m, "rco-25m", "ext-rc0-100m",
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| /kernel/linux/linux-6.6/drivers/clk/sunxi-ng/ |
| D | ccu-sun4i-a10.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
28 #include "ccu-sun4i-a10.h"
34 .m = _SUNXI_CCU_DIV(0, 2),
38 .hw.init = CLK_HW_INIT("pll-core",
50 * With sigma-delta modulation for fractional-N on the audio PLL,
60 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
61 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
67 .m = _SUNXI_CCU_DIV_OFFSET(0, 5, 0),
73 .hw.init = CLK_HW_INIT("pll-audio-base",
[all …]
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| D | ccu-sun5i.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
24 #include "ccu-sun5i.h"
30 .m = _SUNXI_CCU_DIV(0, 2),
34 .hw.init = CLK_HW_INIT("pll-core",
46 * With sigma-delta modulation for fractional-N on the audio PLL,
56 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
57 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
68 .m = _SUNXI_CCU_DIV_OFFSET(0, 5, 0),
74 .hw.init = CLK_HW_INIT("pll-audio-base",
[all …]
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| D | ccu-suniv-f1c100s.c | 1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
25 #include "ccu-suniv-f1c100s.h"
33 .m = _SUNXI_CCU_DIV(0, 2),
39 .hw.init = CLK_HW_INIT("pll-cpu", "osc24M",
55 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
58 0, 5, /* M */
63 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
66 0, 4, /* M */
75 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/sunxi-ng/ |
| D | ccu-sun4i-a10.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
26 #include "ccu-sun4i-a10.h"
32 .m = _SUNXI_CCU_DIV(0, 2),
36 .hw.init = CLK_HW_INIT("pll-core",
48 * With sigma-delta modulation for fractional-N on the audio PLL,
58 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
59 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
65 .m = _SUNXI_CCU_DIV_OFFSET(0, 5, 0),
71 .hw.init = CLK_HW_INIT("pll-audio-base",
[all …]
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| D | ccu-sun5i.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
24 #include "ccu-sun5i.h"
30 .m = _SUNXI_CCU_DIV(0, 2),
34 .hw.init = CLK_HW_INIT("pll-core",
46 * With sigma-delta modulation for fractional-N on the audio PLL,
56 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
57 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
68 .m = _SUNXI_CCU_DIV_OFFSET(0, 5, 0),
74 .hw.init = CLK_HW_INIT("pll-audio-base",
[all …]
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| D | ccu-suniv-f1c100s.c | 1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
24 #include "ccu-suniv-f1c100s.h"
32 .m = _SUNXI_CCU_DIV(0, 2),
38 .hw.init = CLK_HW_INIT("pll-cpu", "osc24M",
54 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
57 0, 5, /* M */
62 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
65 0, 4, /* M */
74 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
[all …]
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| D | ccu-sun50i-h6-r.c | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
18 #include "ccu-sun50i-h6-r.h"
21 * Information about AR100 and AHB/APB clocks in R_CCU are gathered from
26 "iosc", "pll-periph0" };
52 static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &ar100_clk.common.hw, 1, 1, 0);
54 static SUNXI_CCU_M(r_apb1_clk, "r-apb1", "r-ahb", 0x00c, 0, 2, 0);
70 .hw.init = CLK_HW_INIT_PARENTS("r-apb2",
84 static SUNXI_CCU_GATE(r_apb1_timer_clk, "r-apb1-timer", "r-apb1",
86 static SUNXI_CCU_GATE(r_apb1_twd_clk, "r-apb1-twd", "r-apb1",
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/stm32/ |
| D | st,mlahb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: STMicroelectronics STM32 ML-AHB interconnect bindings
10 - Fabien Dessenne <fabien.dessenne@st.com>
11 - Arnaud Pouliquen <arnaud.pouliquen@st.com>
14 These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects
15 a Cortex-M subsystem with dedicated memories. The MCU SRAM and RETRAM memory
17 using different buses (see [2]): balancing the Cortex-M firmware accesses
23 - $ref: /schemas/simple-bus.yaml#
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/stm32/ |
| D | st,mlahb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 ML-AHB interconnect
10 - Fabien Dessenne <fabien.dessenne@foss.st.com>
11 - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
14 These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects
15 a Cortex-M subsystem with dedicated memories. The MCU SRAM and RETRAM memory
17 using different buses (see [2]): balancing the Cortex-M firmware accesses
23 - $ref: /schemas/simple-bus.yaml#
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/qcom/ |
| D | qcom,geni-se.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
23 - qcom,geni-se-qup
24 - qcom,geni-se-i2c-master-hub
30 clock-names:
38 "#address-cells":
41 "#size-cells":
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/soc/qcom/ |
| D | qcom,geni-se.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Mukesh Savaliya <msavaliy@codeaurora.org>
11 - Akash Asthana <akashast@codeaurora.org>
24 - qcom,geni-se-qup
30 clock-names:
32 - const: m-ahb
33 - const: s-ahb
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/sunxi/ |
| D | clk-sun9i-core.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2014 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
9 #include <linux/clk-provider.h>
14 #include "clk-factors.h"
18 * sun9i_a80_get_pll4_factors() - calculates n, p, m factors for PLL4
20 * rate = (parent_rate * n >> p) / (m + 1);
23 * p and m are named div1 and div2 in Allwinner's SDK
29 int m = 1; in sun9i_a80_get_pll4_factors() local
33 n = DIV_ROUND_UP(req->rate, 6000000); in sun9i_a80_get_pll4_factors()
[all …]
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| D | clk-sunxi.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
19 #include "clk-factors.h"
27 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
29 * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
37 /* Normalize value to a 6M multiple */ in sun4i_get_pll1_factors()
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
41 /* m is always zero for pll1 */ in sun4i_get_pll1_factors()
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/sunxi/ |
| D | clk-sun9i-core.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2014 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
9 #include <linux/clk-provider.h>
14 #include "clk-factors.h"
18 * sun9i_a80_get_pll4_factors() - calculates n, p, m factors for PLL4
20 * rate = (parent_rate * n >> p) / (m + 1);
23 * p and m are named div1 and div2 in Allwinner's SDK
29 int m = 1; in sun9i_a80_get_pll4_factors() local
33 n = DIV_ROUND_UP(req->rate, 6000000); in sun9i_a80_get_pll4_factors()
[all …]
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| D | clk-sunxi.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
19 #include "clk-factors.h"
27 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
29 * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
37 /* Normalize value to a 6M multiple */ in sun4i_get_pll1_factors()
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
41 /* m is always zero for pll1 */ in sun4i_get_pll1_factors()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/ |
| D | clk-aspeed.c | 1 // SPDX-License-Identifier: GPL-2.0+
4 #define pr_fmt(fmt) "clk-aspeed: " fmt
13 #include <dt-bindings/clock/aspeed-clock.h>
15 #include "clk-aspeed.h"
49 [ASPEED_CLK_GATE_ECLK] = { 0, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
50 [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
51 [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
52 [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */
53 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */
54 [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/ |
| D | clk-aspeed.c | 1 // SPDX-License-Identifier: GPL-2.0+
4 #define pr_fmt(fmt) "clk-aspeed: " fmt
13 #include <dt-bindings/clock/aspeed-clock.h>
15 #include "clk-aspeed.h"
49 [ASPEED_CLK_GATE_ECLK] = { 0, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
50 [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
51 [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
52 [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */
53 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */
54 [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/imx/ |
| D | clk-imx27.c | 1 // SPDX-License-Identifier: GPL-2.0
3 #include <linux/clk-provider.h>
9 #include <dt-bindings/clock/imx27-clock.h>
41 "ahb", "ipg", "per1_div", "per2_div",
43 "nfc_div", "mshc_div", "vpu_div", "60m",
70 clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2); in _mx27_clocks_init()
71 clk[IMX27_CLK_IPG] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); in _mx27_clocks_init()
73 clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4); in _mx27_clocks_init()
74 clk[IMX27_CLK_IPG] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1); in _mx27_clocks_init()
77 clk[IMX27_CLK_MSHC_DIV] = imx_clk_divider("mshc_div", "ahb", CCM_PCDR0, 0, 6); in _mx27_clocks_init()
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/imx/ |
| D | clk-imx27.c | 1 // SPDX-License-Identifier: GPL-2.0
3 #include <linux/clk-provider.h>
9 #include <dt-bindings/clock/imx27-clock.h>
40 "ahb", "ipg", "per1_div", "per2_div",
42 "nfc_div", "mshc_div", "vpu_div", "60m",
69 clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2); in _mx27_clocks_init()
70 clk[IMX27_CLK_IPG] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); in _mx27_clocks_init()
72 clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4); in _mx27_clocks_init()
73 clk[IMX27_CLK_IPG] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1); in _mx27_clocks_init()
76 clk[IMX27_CLK_MSHC_DIV] = imx_clk_divider("mshc_div", "ahb", CCM_PCDR0, 0, 6); in _mx27_clocks_init()
[all …]
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| /kernel/linux/linux-6.6/arch/arm/mach-ep93xx/ |
| D | ep93xx-regs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
9 * fe800000 5M per-platform mappings
10 * fed00000 80800000 2M APB
11 * fef00000 80000000 1M AHB
|
| /kernel/linux/linux-5.10/arch/arm/mach-ep93xx/include/mach/ |
| D | ep93xx-regs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
13 * fe800000 5M per-platform mappings
14 * fed00000 80800000 2M APB
15 * fef00000 80000000 1M AHB
|
| /kernel/linux/linux-6.6/drivers/clk/microchip/ |
| D | clk-mpfs.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved.
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/microchip,mpfs-clock.h>
99 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; in mpfs_clk_msspll_recalc_rate()
100 void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; in mpfs_clk_msspll_recalc_rate()
101 void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR; in mpfs_clk_msspll_recalc_rate()
117 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; in mpfs_clk_msspll_round_rate()
118 void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; in mpfs_clk_msspll_round_rate()
130 msspll_hw->flags); in mpfs_clk_msspll_round_rate()
[all …]
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| /kernel/linux/linux-6.6/sound/soc/rockchip/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
6 Say Y or M if you want to add support for codecs attached to
15 Say Y or M if you want to add support for I2S driver for
24 Say Y or M if you want to add support for the I2S/TDM driver for
26 interface between the AHB bus and the I2S bus, and support up to a
36 Say Y or M if you want to add support for PDM driver for
45 Say Y or M if you want to add support for SPDIF driver for
56 Say Y or M here if you want to add support for SoC audio on Rockchip
65 Say Y or M here if you want to add support for SoC audio on Rockchip
77 Say Y or M here if you want to add support for SoC audio on Rockchip
[all …]
|