| /kernel/linux/linux-5.10/drivers/spi/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
13 dynamic device discovery; some are even write-only or read-only.
17 chips, analog to digital (and d-to-a) converters, and more.
36 # MASTER side ... talking to discrete SPI slave chips including microcontrollers
40 # bool "SPI Master Support"
44 If your system has an master-capable SPI controller (which
56 by providing a high-level interface to send memory-like commands.
58 comment "SPI Master Controller Drivers"
101 This selects a driver for the AT91 USART Controller as SPI Master,
109 This enables support for the Quad SPI controller in master mode.
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| D | spi-qup.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2008-2014, The Linux foundation. All rights reserved.
19 #include <linux/dma-mapping.h>
116 #define SPI_MAX_XFER (SZ_64K - 64)
118 /* high speed mode is when bus rate is greater then 26MHz */
149 int mode; member
158 u32 opflag = readl_relaxed(controller->base + QUP_OPERATIONAL); in spi_qup_is_flag_set()
163 static inline bool spi_qup_is_dma_xfer(int mode) in spi_qup_is_dma_xfer() argument
165 if (mode == QUP_IO_M_MODE_DMOV || mode == QUP_IO_M_MODE_BAM) in spi_qup_is_dma_xfer()
174 return controller->n_words * controller->w_size; in spi_qup_len()
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| D | spi-pic32.c | 1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/dma-mapping.h>
58 #define CTRL_MSTEN BIT(5) /* enable master mode */
72 #define CTRL_FRMEN BIT(31) /* enable framing mode */
88 #define CTRL2_TX_UR_EN BIT(10) /* Enable int on Tx under-run */
89 #define CTRL2_RX_OV_EN BIT(11) /* Enable int on Rx over-run */
103 struct spi_master *master; member
105 u32 speed_hz; /* spi-clk rate */
106 u32 mode; member
125 writel(CTRL_ON | CTRL_SIDL, &pic32s->regs->ctrl_set); in pic32_spi_enable()
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| D | spi-sifive.c | 1 // SPDX-License-Identifier: GPL-2.0
5 // SiFive SPI controller driver (master mode only)
27 #define SIFIVE_SPI_REG_SCKMODE 0x04 /* Serial clock mode */
30 #define SIFIVE_SPI_REG_CSMODE 0x18 /* Chip select mode */
96 struct completion done; /* wake-up from interrupt */
101 iowrite32(value, spi->regs + offset); in sifive_spi_write()
106 return ioread32(spi->regs + offset); in sifive_spi_read()
126 /* Exit specialized memory-mapped SPI flash mode */ in sifive_spi_init()
131 sifive_spi_prepare_message(struct spi_master *master, struct spi_message *msg) in sifive_spi_prepare_message() argument
133 struct sifive_spi *spi = spi_master_get_devdata(master); in sifive_spi_prepare_message()
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| D | spi-omap2-mcspi.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
15 #include <linux/dma-mapping.h>
30 #include <linux/platform_data/spi-omap2-mcspi.h>
47 /* per-channel banks, 0x14 bytes each, first is: */
54 /* per-register bitmasks: */
120 struct spi_master *master; member
138 u16 mode; member
144 static inline void mcspi_write_reg(struct spi_master *master, in mcspi_write_reg() argument
147 struct omap2_mcspi *mcspi = spi_master_get_devdata(master); in mcspi_write_reg()
149 writel_relaxed(val, mcspi->base + idx); in mcspi_write_reg()
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| D | spi-ppc4xx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
39 #include <asm/dcr-regs.h>
41 /* bits in mode register - bit 0 is MSb */
54 * SPI_PPC4XX_MODE_RD = 0 means "MSB first" - this is the normal mode
55 * SPI_PPC4XX_MODE_RD = 1 means "LSB first" - this is bit-reversed mode
92 u8 mode; member
103 * CDM = (OPBCLK/4*SCPClkOut) - 1
129 struct spi_master *master; member
135 u8 mode; member
143 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", in spi_ppc4xx_txrx()
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| D | spi-fsl-spi.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * CPM SPI and QE buffer descriptors mode support:
19 #include <linux/dma-mapping.h>
45 #include "spi-fsl-lib.h"
46 #include "spi-fsl-cpm.h"
47 #include "spi-fsl-spi.h"
81 if (dev->of_node) { in fsl_spi_get_type()
82 match = of_match_node(of_fsl_spi_match, dev->of_node); in fsl_spi_get_type()
83 if (match && match->data) in fsl_spi_get_type()
84 return ((struct fsl_spi_match_data *)match->data)->type; in fsl_spi_get_type()
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| D | spi-fsl-espi.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
23 #define ESPI_SPMODE 0x00 /* eSPI mode register */
29 #define ESPI_SPMODE0 0x20 /* eSPI cs0 mode register */
33 /* eSPI Controller mode register definitions */
39 /* eSPI Controller CS mode register definitions */
54 /* Default mode/csmode for eSPI controller */
118 return ioread32be(espi->reg_base + offset); in fsl_espi_read_reg()
123 return ioread16be(espi->reg_base + offset); in fsl_espi_read_reg16()
128 return ioread8(espi->reg_base + offset); in fsl_espi_read_reg8()
134 iowrite32be(val, espi->reg_base + offset); in fsl_espi_write_reg()
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| D | spi-dln2.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for the Diolan DLN-2 USB-SPI adapter
81 struct spi_master *master; member
93 u16 mode; member
110 tx.port = dln2->port; in dln2_spi_enable()
114 len -= sizeof(tx.wait_for_completion); in dln2_spi_enable()
120 return dln2_transfer_tx(dln2->pdev, cmd, &tx, len); in dln2_spi_enable()
128 * Ex: cs_mask = 0x03 -> CS0 & CS1 will be selected and the next WR/RD operation
138 tx.port = dln2->port; in dln2_spi_cs_set()
147 return dln2_transfer_tx(dln2->pdev, DLN2_SPI_SET_SS, &tx, sizeof(tx)); in dln2_spi_cs_set()
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| D | spi-lantiq-ssc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011-2015 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
4 * Copyright (C) 2016 Hauke Mehrtens <hauke@hauke-m.de>
53 #define LTQ_SPI_CLC_SMC_S 16 /* Clock divider for sleep mode */
55 #define LTQ_SPI_CLC_RMC_S 8 /* Clock divider for normal run mode */
70 #define LTQ_SPI_CON_EM BIT(24) /* Echo mode */
93 #define LTQ_SPI_STAT_ME BIT(7) /* Mode error flag */
94 #define LTQ_SPI_STAT_MS BIT(1) /* Master/slave select bit */
108 #define LTQ_SPI_WHBSTATE_SETME BIT(7) /* Set mode error flag */
109 #define LTQ_SPI_WHBSTATE_CLRME BIT(6) /* Clear mode error flag */
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| D | spi-gpio.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * SPI master driver using generic bitbanged GPIO
21 * This bitbanging SPI master driver should help make systems usable
26 * platform_device->driver_data ... points to spi_gpio
28 * spi->controller_state ... reserved for bitbang framework code
30 * spi->master->dev.driver_data ... points to spi_gpio->bitbang
41 /*----------------------------------------------------------------------*/
48 * - The slow generic way: set up platform_data to hold the GPIO
52 * - The quicker inlined way: only helps with platform GPIO code
63 * #include "spi-gpio.c"
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| D | spi-synquacer.c | 1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright (c) 2015-2018 Socionext Inc.
6 // Copyright (c) 2018-2019 Linaro Ltd.
108 (SYNQUACER_HSSPI_FIFO_DEPTH - SYNQUACER_HSSPI_FIFO_TX_THRESHOLD)
126 unsigned int mode; member
143 u32 len = readl(sspi->regs + SYNQUACER_HSSPI_REG_DMSTATUS); in read_fifo()
147 len = min(len, sspi->rx_words); in read_fifo()
149 switch (sspi->bpw) { in read_fifo()
151 u8 *buf = sspi->rx_buf; in read_fifo()
153 ioread8_rep(sspi->regs + SYNQUACER_HSSPI_REG_RX_FIFO, in read_fifo()
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| /kernel/linux/linux-6.6/drivers/spi/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
13 dynamic device discovery; some are even write-only or read-only.
17 chips, analog to digital (and d-to-a) converters, and more.
36 # MASTER side ... talking to discrete SPI slave chips including microcontrollers
40 # bool "SPI Master Support"
44 If your system has an master-capable SPI controller (which
56 by providing a high-level interface to send memory-like commands.
58 comment "SPI Master Controller Drivers"
79 Altera SPI master controller. The SPI master is connected
86 This enables master mode support for the SPIFC (SPI flash
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| D | spi-synquacer.c | 1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright (c) 2015-2018 Socionext Inc.
6 // Copyright (c) 2018-2019 Linaro Ltd.
108 (SYNQUACER_HSSPI_FIFO_DEPTH - SYNQUACER_HSSPI_FIFO_TX_THRESHOLD)
126 unsigned int mode; member
143 u32 len = readl(sspi->regs + SYNQUACER_HSSPI_REG_DMSTATUS); in read_fifo()
147 len = min(len, sspi->rx_words); in read_fifo()
149 switch (sspi->bpw) { in read_fifo()
151 u8 *buf = sspi->rx_buf; in read_fifo()
153 ioread8_rep(sspi->regs + SYNQUACER_HSSPI_REG_RX_FIFO, in read_fifo()
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| /kernel/linux/linux-5.10/drivers/staging/greybus/ |
| D | spilib.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright 2014-2016 Google Inc.
6 * Copyright 2014-2016 Linaro Ltd.
28 u16 mode; member
41 #define GB_SPI_STATE_MSG_ERROR ((void *)-1)
47 return gb_connection_get_data(spi->connection); in get_master_from_spi()
54 data_max -= sizeof(struct gb_spi_transfer_request); in tx_header_fit_operation()
65 data_max -= sizeof(struct gb_spi_transfer_response); in calc_rx_xfer_size()
68 rx_xfer_size = data_max - rx_size; in calc_rx_xfer_size()
86 data_max -= sizeof(struct gb_spi_transfer_request); in calc_tx_xfer_size()
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| /kernel/linux/linux-6.6/drivers/staging/greybus/ |
| D | spilib.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright 2014-2016 Google Inc.
6 * Copyright 2014-2016 Linaro Ltd.
28 u16 mode; member
41 #define GB_SPI_STATE_MSG_ERROR ((void *)-1)
47 return gb_connection_get_data(spi->connection); in get_master_from_spi()
54 data_max -= sizeof(struct gb_spi_transfer_request); in tx_header_fit_operation()
65 data_max -= sizeof(struct gb_spi_transfer_response); in calc_rx_xfer_size()
68 rx_xfer_size = data_max - rx_size; in calc_rx_xfer_size()
86 data_max -= sizeof(struct gb_spi_transfer_request); in calc_tx_xfer_size()
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| /kernel/linux/linux-5.10/drivers/i3c/ |
| D | master.c | 1 // SPDX-License-Identifier: GPL-2.0
26 * i3c_bus_maintenance_lock - Lock the bus for a maintenance operation
31 * - enabling/disabling slave events
32 * - re-triggering DAA
33 * - changing the dynamic address of a device
34 * - relinquishing mastership
35 * - ...
43 down_write(&bus->lock); in i3c_bus_maintenance_lock()
47 * i3c_bus_maintenance_unlock - Release the bus lock after a maintenance
57 up_write(&bus->lock); in i3c_bus_maintenance_unlock()
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| /kernel/linux/linux-5.10/Documentation/networking/ |
| D | ipvlan.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 exception of using L3 for mux-ing /demux-ing among slaves. This property makes
14 the master device share the L2 with it's slave devices. I have developed this
34 ip link add link <master> name <slave> type ipvlan [ mode MODE ] [ FLAGS ]
36 MODE: l3 (default) | l3s | l2
41 (a) Following will create IPvlan link with eth0 as master in
42 L3 bridge mode::
45 (b) This command will create IPvlan link in L2 bridge mode::
47 bash# ip link add link eth0 name ipvl0 type ipvlan mode l2 bridge
49 (c) This command will create an IPvlan device in L2 private mode::
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| /kernel/linux/linux-6.6/Documentation/networking/ |
| D | ipvlan.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 exception of using L3 for mux-ing /demux-ing among slaves. This property makes
14 the master device share the L2 with its slave devices. I have developed this
34 ip link add link <master> name <slave> type ipvlan [ mode MODE ] [ FLAGS ]
36 MODE: l3 (default) | l3s | l2
41 (a) Following will create IPvlan link with eth0 as master in
42 L3 bridge mode::
45 (b) This command will create IPvlan link in L2 bridge mode::
47 bash# ip link add link eth0 name ipvl0 type ipvlan mode l2 bridge
49 (c) This command will create an IPvlan device in L2 private mode::
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/ata/ |
| D | cortina,gemini-sata-bridge.txt | 3 The Gemini SATA bridge in a SoC-internal PATA to SATA bridge that
8 - compatible: should be
9 "cortina,gemini-sata-bridge"
10 - reg: registers and size for the block
11 - resets: phandles to the reset lines for both SATA bridges
12 - reset-names: must be "sata0", "sata1"
13 - clocks: phandles to the compulsory peripheral clocks
14 - clock-names: must be "SATA0_PCLK", "SATA1_PCLK"
15 - syscon: a phandle to the global Gemini system controller
16 - cortina,gemini-ata-muxmode: tell the desired multiplexing mode for
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| /kernel/linux/linux-6.6/drivers/i3c/ |
| D | master.c | 1 // SPDX-License-Identifier: GPL-2.0
27 * i3c_bus_maintenance_lock - Lock the bus for a maintenance operation
32 * - enabling/disabling slave events
33 * - re-triggering DAA
34 * - changing the dynamic address of a device
35 * - relinquishing mastership
36 * - ...
44 down_write(&bus->lock); in i3c_bus_maintenance_lock()
48 * i3c_bus_maintenance_unlock - Release the bus lock after a maintenance
58 up_write(&bus->lock); in i3c_bus_maintenance_unlock()
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| /kernel/linux/linux-6.6/drivers/media/dvb-frontends/drx39xyj/ |
| D | drx_dap_fasi.h | 2 Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
48 /*-------- compilation control switches --------------------------------------*/
53 /*-------- Required includes -------------------------------------------------*/
57 /*-------- Defines, configuring the API --------------------------------------*/
98 #error At least one of short- or long-addressing format must be allowed.
103 * Single/master multi master setting
106 * Comments about SINGLE MASTER/MULTI MASTER modes:
108 * Consider the two sides:1) the master and 2)the slave.
110 * Master:
112 * + single master mode means no use of repeated starts
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| /kernel/linux/linux-5.10/drivers/media/dvb-frontends/drx39xyj/ |
| D | drx_dap_fasi.h | 2 Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
48 /*-------- compilation control switches --------------------------------------*/
53 /*-------- Required includes -------------------------------------------------*/
57 /*-------- Defines, configuring the API --------------------------------------*/
98 #error At least one of short- or long-addressing format must be allowed.
103 * Single/master multi master setting
106 * Comments about SINGLE MASTER/MULTI MASTER modes:
108 * Consider the two sides:1) the master and 2)the slave.
110 * Master:
112 * + single master mode means no use of repeated starts
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| /kernel/linux/linux-6.6/Documentation/networking/device_drivers/ethernet/ti/ |
| D | cpsw_switchdev.rst | 1 .. SPDX-License-Identifier: GPL-2.0
17 ip -d link show dev sw0p1 | grep switchid
23 Dual mac mode
26 - The new (cpsw_new.c) driver is operating in dual-emac mode by default, thus
30 - optimized promiscuous mode: The P0_UNI_FLOOD (both ports) is enabled in
32 So, Ports in promiscuous mode will keep possibility of mcast and vlan
34 to the same bridge, but without enabling "switch" mode, or to different
36 - learning disabled on ports as it make not too much sense for
37 segregated ports - no forwarding in HW.
38 - enabled basic support for devlink.
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| /kernel/linux/linux-5.10/Documentation/networking/device_drivers/ethernet/ti/ |
| D | cpsw_switchdev.rst | 1 .. SPDX-License-Identifier: GPL-2.0
17 ip -d link show dev sw0p1 | grep switchid
23 Dual mac mode
26 - The new (cpsw_new.c) driver is operating in dual-emac mode by default, thus
30 - optimized promiscuous mode: The P0_UNI_FLOOD (both ports) is enabled in
32 So, Ports in promiscuous mode will keep possibility of mcast and vlan
34 to the same bridge, but without enabling "switch" mode, or to different
36 - learning disabled on ports as it make not too much sense for
37 segregated ports - no forwarding in HW.
38 - enabled basic support for devlink.
[all …]
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